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RTL design,Physical design,ASIC,FPGA,Computer architecture, MEMS

Location:
California
Posted:
June 24, 2017

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Resume:

VIJAY KOUSHIK BELAGUR SUDEESH

*** * ******* ****, **** 1022, Mountain view, California - 94043

972-***-**** ac0zyn@r.postjobfree.com https://in.linkedin.com/in/vijaykoushik

OBJECTIVE: MS EE Graduate skilled in RTL design, Physical design, EDA and scripting seeking entry level opportunities

In Digital VLSI. (ASIC/FPGA, computer architecture or MEMS).

EDUCATION:

Master of Science in Electrical Engineering

The University of Texas at Dallas, Richardson, Texas

August 2015 – May 2017

GPA: 3.87 / 4.0

Bachelor of Engineering in Electronics and Communications Engineering

Bangalore Institute of Technology, Bangalore, India

June 2011 – May 2015 Percentage: 81.56%

TECHNICAL SKILLS:

Programming languages: C, Verilog, VHDL, Perl, Python, Tcl, shell scripting.

Software tools : Matlab, LabVIEW, Xilinx (ISE, Vivado), Modelsim, Tetramax (for ATPG), GNU compiler, HSpice.

Physical design tools : Cadence (Specter, Virtuoso, Assura, Encounter); Synopsys (Design vision, SiliconSmart, Primetime, IC Compiler).

Miscellaneous : PCB design (Diptrace), Linux, GIT, Makefile, lab tools (Oscilloscope, Network Analyzer, Function generator).

RELEVANT COURSEWORK:

Physical Design Automation Computer Architecture Analog Computing ASIC Design Analog IC Design

FPGAs and Reconfigurable Systems Testing and Testable design (DFT, BIST) Wireless Communication Lab VLSI Design

ACADEMIC PROJECTS:

Machine learning in semiconductor fabrication (January 2017 – May 2017 )

Designed a feature selection algorithm using a Genetic algorithm to build a regression model using MARS to reduce the testing cost of analog and RF chips. The model achieved 98% accuracy on industrial data of 12000 chips compacting tests by 28%.

Scan cell insertion; and test pattern generation to determine test vectors, and identifying stuck at faults and fault coverage.

Reconfigurable Systems –FPGA Softcore (September 2016 – December 2016)

Analysis and study of an analog accelerator with FPGA to achieve low power, high-performance analog computing model.

Design and implementation of a customizable overlay microprocessor on FPGA with keyboard and VGA interface.

RTL design, synthesis and physical design implementation of DSP ASIC chip

•A. Specification development and architecture design for semi-custom programmable audio processor ASIC chip. It involved RTL design, logic simulation, gate level synthesis, schematic & layout design (DRC &LVS), placement & routing using IC compiler.

•B. Created Standard cell library to Implement the physical design of ALU and performed functional verification and STA.

MIPS based architecture design for distributed computing in physical network and data sharing (March 2016 – May 2016)

•Verilog implementation of MIPS-based pipelined architecture to perform low-level computation, on-chip and coordinate high-level computation in a cloud, in a physical network established with BLE and Wi-Fi based beacons.

Analog IC Design: Two-stage amplifier (March 2016 – May 2016)

Designed a differential input; single-ended output Two-Stage amplifier in 0.35- m CMOS. The bias currents were generated by the self-biased bandgap current source and current mirrors. It included a start-up circuit in the self-biased current source.

Wireless communication, Laboratory experience (August 2015 – December 2015)

•Developed code for performing frame synchronization, channel estimation and equalization using Matlab and LabVIEW. Simulated baseband digital modem for various modulation schemes on a software defined radio and implemented a Wi-Fi sniffer.

Simulated annealing based algorithm for partition and placement (September 2015 – November 2015)

A. Implemented a parser and data structure in C for bi-partitioning of netlists to obtain minimum cut size on IBM benchmarks.

B. Implemented a fixed die standard cell placer engine based on Timberwolf method to minimize total wire length on the chip.

Industrial automation using IOT (December 2014 – March 2015)

•Designed an ARM-based system to enable inter-device communication and data sharing. It executed tasks autonomously or with minimal user interaction by monitoring data and comparing it with previously recorded values in the database.

ACTIVITIES:

Mini projects using embedded hardware

•Programmed microcontrollers (Raspberry Pi, Arduino, atmega) to operate and interface sensors and peripheral devices.

•Built simple autonomous robots. Implemented basic home automation system and health monitoring system.

Member - Rotaract club, Bangalore

•Tutored high school students in basic science. Organized Health camps and coordinated a Sports and Cultural fest.

WORK EXPERIENCE:

Graduate research assistant, Micronex (MEMS) Lab – UT Dallas (March 2016 – May 2017)

•Design, fabrication (Lithography, etching, deposition) of MEMS devices like piezo resistors, resonators, accelerometers etc.

•Worked on electrostatic MEMS motors. Built PCBs to test and analyze the performance of MEMS devices.

Work Authorization & availability: F1 Student Visa (EAD) JUNE 2017



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