Tanik Rudra Prasad

Phone: +1-978-***-****; Email: ac0miz@r.postjobfree.com

**-** **** ****** ****, Lowell, MA 01854

Objective

Looking for a Full-time role in Electrical engineering.

Education

MS, Electrical and Computer Engineering, University of Massachusetts Lowell June2017

BE, Electronics and Communication Engineering, Visvesvaraya Technological University June 2015

Skills

Programming: C, VHDL and VERILOG, Python.

Tools & Software: MATLAB, LabVIEW, XILINX ISE, CADENCE VIRTUOSO, LT Spice, MULTISIM, Auto CAD

Coursework: VLSI Design, VLSI Fabrication, Advanced VLSI, Mixed Signal VLSI, VHDL-VERILOG, FPGA Design, Verification of Digital Systems, Computer Architecture and Design, Microelectronic Circuits- Digital and Analog Communication, Power Electronics, CMOS-VLSI, Logic Design,

Experience

Engineering Intern, ABB 05/2014-06/2014

Worked on Remote terminal units to supervise and control the switchyard equipment and used SCADA HMI for data control and acquisition.

Worked on achieving an accurate, efficient and fast monitoring of digital and analog data from the switchyard of the substations and secured power transfer.

Publication

The performance of multi-layer neural network on face recognition system

2nd International Conference on Contemporary Computing and Informatics (IC3I)

Year: 2016 Pages: 414 - 420, DOI: 10.1109/IC3I.2016.7918000,Electronic ISBN: 978-1-5090-5256-1

Authors: M. J. Yashaswini; V. S. Vishnu; B N Annapurna; Tanik R Prasad

Projects

Design of Different type of Architecture Data path

Designed different architecture data path mainly reference data path, parallel data path, pipelined data path, parallel-pipelined data path in 45nm CMOS PDK technology and made a comparative study of power savings among each of the data path and evaluated it.

Design of a 4b*4b SRAM

Designed a 4b*4b SRAM using row and column decoder operating at nominal voltage in 45nm CMOS PDK technology and performed power analysis and determined the data retention voltage for the SRAM array.

Design and Comparison of 16/8 Parallel and Parallel Pipelined Decomposition Multiplier

Designed a 16 bit and 8-bit parallel decomposition multiplier and 16 and 8-bit parallel pipelined decomposition multiplier in 45nm CMOS PDK technology and compared the power consumptions between the circuits.

Design of 4-Bit Ripple Carry Adder using 24T Full Adder

Designed the schematic and layout of 4-bit ripple carry adder using 24T full adder in CMOS 0.6um technology.

Design of Low Drop Out Linear Voltage Regulator

Designed a operational trans-conductance amplifier in the first stage. In the second stage cascoded the OTA with current mirrors to improve the gain. In the third stage added sizable PMOS transistor to improve the gain and stabilize the output voltage. The designs were all constructed in 0.5nm CMOS technology.

Design of 3-stage Operational Amplifier

Designed an operational amplifier in 0.5nm CMOS technology to meet the necessary specifications. Constructed a differential pair using current mirror to obtain a high gain output. Implemented the buffer stage using a push-pull amplifier. Built bias boost and CMRR boost to stabilize current and increase gain in the circuit.

Study on Graphene Battery Technology

Performed a literature study on concept of graphene used in batteries as an active material to provide a scope for future development in battery technology to store enormous amount of power and charge within few seconds.