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Engineer Process

Location:
Santa Clara, CA
Posted:
July 02, 2013

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Resume:

Robert C. Dinsmore III

? Phone: 408-***-**** ? Email: *********@*****.***

SUMMARY

Senior research engineer and Ph.D. physicist with over 4 years of industry

experience developing semiconductor capital equipment hardware and

processes. Experienced with managing R&D projects to support the

development of industry leading products through all stages of the Product

Life Cycle. Accomplished at identifying problems and risks and skilled at

providing innovative solutions to address them.

Highlights

. Hardware Development: Performed fundamental experiments to understand

plasma behavior in a chamber and designed new hardware to improve

chamber performance.

. Process Development: Delivered key understandings of chamber behavior

to guide future process directions and developed new wafer level

processes and chamber clean processes for a new preclean chamber.

. Project Management: Led all aspects of defect reduction efforts for a

CVD product including initial chamber install, coordinating resources,

planning all R&D activities for a team of 3 process engineers, and

presenting clear reports to the program manager.

PROFESSIONAL EXPERIENCE

Senior Process Engineer Applied Materials July 2010 - Present

Metal Deposition Products: Santa Clara CA

Defect Reduction and Wafer

Level Packaging

. Developed new process and hardware IP for wafer level packaging Dual

frequency RF clean chamber resulting in 3 patents and a winning

product

. Performed a fundamental study of process-hardware interaction in a new

metal CVD chamber to optimize process and kit life during development

creating a knowledge base that is a clear differentiator to our

customers

. Utilized surface and cross section techniques to solve device and

process kit failures while defining the process window in new CCP

Etch, CVD and ALD chambers

Process TD Engineer Intel March 2009 - April 2010

Portland Technology Hillsboro, OR

Development

Single Wafer Cleans

. Maintained the quality and output of a DNS SU3800 Single Wafer Clean

processing tool by monitoring SPC and fault detection data to

troubleshoot potential problems before they occurred

. Coordinated the daily operations of a 12 tool module by managing

factory technicians, scheduling maintenance activities, evaluating

production material subjected to tool aborts and tool errors, and

maintaining high throughput

. Collaborated with Thin Film Module to develop a reliable TiN film for

monitoring SPM etch rate that resulted in better chamber matching and

less down time for Etch Rate due to incoming wafer quality

Research Assistant Department of Physics 2003 - 2009

Urbana IL

University of

Illinois

. Led a team of colleagues on a multi-approach initiative to determine

the reason for the sudden failure of our sputtering procedure and to

develop a new process for fabricating high quality MoGe

superconducting thin films

. Constructed and tested a new cryogenic, low-noise microwave system to

enable high frequency transport measurements and assisted others with

using this equipment in their research

. Performed numerical simulations in MATLAB to confirm the theory and

explain the phenomena observed in device characterization resulting in

a high quality publication

EDUCATION and CERTIFICATION

UNIVERSITY OF ILLINOIS AT URBANA-CHAMPAIGN (UIUC) Ph.D. in Physics

Advisor: Alexey Bezryadin Thesis Title: Microwave

Response in Superconducting Nanowires

Certificate: Strategic Technology Management

NORTHEASTERN UNIVERSITY M.S. in Physics

UNIVERSITY OF MASSACHUSSETTS AT AMHERST B.S. Chemistry and

Physics

SKILLS

Instrumentation

. Industrial Semiconductor Tool Maintenance and troubleshooting: Single

Wafer Cleans, RF PVD, RF Etch, Metal CVD and Metal ALD, Applied

Materials 300mm Endura and Producer platforms

. Electronic Transport Measurements: Design and testing of DC and

Microwave Transport Measurement, Network Analyzer, Filtering, Analog

electronics, Low Noise Measurement, lock-in amplifiers, LabView

interfacing, 4 point measurements

. RF Plasma: Matching and ignition optimization, Generators, Arc

detection, OES, Langmuir probe, RGA

. Construction of High Vacuum Systems: Machining, Soldering, Leak

Detection, MFCs, 3He Cryostats, Dilution Refrigerators, Working with

Liquid He and N2, High Field Superconducting Magnets, pressure gauges

Nanofabrication and Metrology

. 300mm Recipe Development: Single Wafer Cleans, RF PVD, RF Etch, Metal

CVD and Metal ALD

. Patterning: Lithography, FIB, Mask design, E-Beam lithography, Wet

etching, Dry Etching

. Film Deposition: PVD, Electron Beam Evaporation, Thermal Evaporation,

(PE)ALD,(PE)CVD

. Other Methods: Molecular Templating using Carbon Nanotubes and DNA,

Graphene, Focused Electron Beam Lithography using a TEM, Nanopore

Sensors

. Metrology: AMAT SEM/EDX, KLA-Tencor Surfscan SP1, SP2 and SP3, SIMS,

ICPMS, GDOES, Raman, XPS, Auger, FTIR, XRD, Spectra Fx, Aleris, Rs,

Rigaku XRF/XRR, Technos XRF/XRR, Thermawave, FIB, TEM/EELS

Computer Skills

. JMP and JMP scripting, DOE, Klarity, SQL, E3, MATLAB, Labview, Origin

Pro, IgorPro, Photoshop, Multisim, Hardware installation, Molecular

dynamics using NAMD, Maya 3D, Quantum Chemistry using GAMESS, C,

Fortran, AMAT CGA, Microsoft Office

ADDITIONAL EXPERIENCE

. Organized and obtained funding for the first of a now annual Intel

presence at the American Physical Society March Meeting Job Fair which

helped recruit dozens of physics PhDs and created great publicity for

Intel.

. Co-founder and first treasurer of the Physics Graduate Student

Association and Coordinated an interdepartmental pig roast attended by

150 physics and chemistry graduate students

. Taught upper level electronics laboratory with an intimate 5:1 student

to instructor ratio for 5 years a Mentored several modern physics

laboratory students while they worked on individual course projects

. Co-founder of I-grads a campus-wide social networking organization for

graduate students which eventually resulted in a graduate college

sponsored monthly social and networking event for graduate students

PATENTS FILED

. Two Piece Transferrable Shutter Disc For a Substrate Process Chamber:

Filed with USPTO July 2012

. In-situ Chamber Clean with Inert Hydrogen Helium Mixture During Wafer

Process Filed with USPTO January 2013

. Finned Shutter Disk For a Substrate Process Chamber : Filed with USPTO

February 2013

PUBLICATIONS AND TALKS

. "Three Innovations for Particle Reduction in PVD Preclean Chamber"

Applied Materials ET Conference 2013, Monterey, CA- Poster

. "Fractional Order Shapiro Steps in Superconducting Nanowires." Appl.

Phys. Lett. 93, 192505 (2008).

. "Current-phase Relationship, Thermal and Quantum Phase Slips in

Superconducting Nanowires Scaffold Created using Adhesive Tape." Nano.

Lett. 9 (5) 1889 (2009).

. "Phase Diagram of the Superconductor-Insulator Transition in One-

Dimensional Wires." Phys. Rev. Lett. 101, 227003 (2008).

. "Zero-Crossing Shapiro Steps in high-TC superconducting-

microstructures tailored by a focused ion beam." Phys. Rev. B. 77,

144501 (2008).

. "Stochastic and deterministic phase slippage in quasi one-dimensional

superconducting nanowires exposed to microwaves" New J.

Phys. 14 043014 (2012)

. "Microwave Response in Superconducting Nanowires" American Physical

Society March Meeting, New Orleans, LA. March 2008

. "AC Josephson Effect in Superconducting Nanowires" Quantum Materials

at the Nanoscale, Frederick Seitz Materials Research Lab, Urbana, IL

April 2008

. "Superconductor Insulator Transition in 1-Dimensional Wires"

University of Illinois at Urbana-Champaign Graduate Student

Colloquium, Urbana, IL. February 2007



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