Manager Development

Jon Bornstein

Email: *********@********.***

Address: ***** ******** **

City: cupertino

State: CA

Zip: 95014

Country: USA

Phone: 408-***-****

Skill Level: Director

Salary Range: $150,000

Primary Skills/Experience:

See Resume

Educational Background:

See Resume

Job History / Details:

JONATHAN G. BORNSTEIN

22460 Starling Court * Cupertino, California 95014

408-***-**** * ************@*******.***

VP / SR DIRECTOR

Semiconductor Technology & Operations

Highly accomplished senior manager with proven track record of directing start-up and established technology companies. Creates models of excellence in semiconductor engineering, operations, manufacturing, material processing, by building strong teams, relationships, and infrastructures. Drives all phases of development from concept to commercialization by providing expertise spanning from technical to business levels. Maximizes performance, profitability, and capabilities, while minimizing time, effort, and costs through strategic planning, technology roadmaps, effective negotiation, and leadership by example.

Strategic Planning * Technology Roadmaps * Thin Films * Integration * Manufacturing * Operations

Foundry Management * Material & Equipment Selection * Process Engineering * Budget Planning

Planar Optics * Design of Experiments * Statistical Process Control * Problem Solving

PROFESSIONAL EXPERIENCE

AMPULSE CORP., (closed due to lack of funding 1/2013) Golden, Colorado * 2/2010 - 1/2013

Start-up Company developing novel thin film solar cell.

Senior Director - Technology Development & Integration

Oversaw and led all aspects of development of thin film photovoltaic cell on flexible metal foil substrate. Managed in-house staff, as well as teams and scientific and engineering efforts at 2 national laboratories in development of thin film materials and processes for device fabrication. Defined weekly tasks for all teams based on key milestones set forth in master technology roadmap.

Achievements:

* Played major role in successful start-up of state-of-the-art solar cell company based on heteroepitaxial monocrystalline thin film on a flexible metallic substrate, spearheading all aspects of corporate technical strategy, and serving as key liaison with Board of Directors and investors.

* Initiated and managed $1.5M overall technical and organizational collaboration with Oak Ridge National Labs and The National Renewable Energy Labs, establishing relationships, routine conference calls, and daily updates with all stakeholders to define architecture and supporting processes.

* Transitioned lab to commercial scale cell pilot-line manufacturing, leading $3M capital equipment vendor selection, design, and qualification for multi-step multi-material deposition on thin metal foil, tool specification, and vendor compliance.

* Transformed scientific research at Oak Ridge National Labs and The National Renewable Energy Labs into fully functional products, directing all phases of technical development including implementation of set of critical material property requirements, testable metrics, and clearly defined specifications.

UNITY SEMICONDUCTOR, (acquired by RAMBUS) Sunnyvale, California * 8/2006 - 2/2010

Start-up Company developing next-generation 3D cross-point nonvolatile memory device based on thin film conductive metal oxide as replacement for flash drives.

Director - Technology Development & Integration

Provided onsite leadership of process and integration organizations comprised of teams of engineers embedded at foundry partner. Directed development of nonvolatile memory device based on thin film conductive metal oxides. Negotiated cost-savings on commercial terms with foundry partner. Managed day-to-day in-house technical support.

Achievements:

* Increased company`s valuation, providing key intellectual property and fully operational technology development and integration function.

* Devised and championed integration architecture, process requirements, and successful implementation at foundry for scalable new memory device.

* Accelerated process development cycle time and access to key equipment, while reducing costs and conflicts, forging strong business and technical relationships with foundry partner.

JONATHAN G. BORNSTEIN

* Page 2 *

************@*******.***

BRION CORP., (acquired by ASML) Santa Clara, California * 8/2003 - 8/2006

Worldwide leader in computational lithography and OPC; wholly owned subsidiary of ASML.

Director - Engineering Operations

Coordinated and led all development and manufacturing of custom server (Tachyon), and sensor-based aerial imaging system for deep-UV photolithography. Directed all corporate operations including manufacturing, logistics, procurement, outsourcing, and IT. Managed all relationships and activities with value added resellers and multiple silicon foundries.

Achievements:

* Reversed poor reliability and customer satisfaction with company-built servers, initiating and directing strategic transition from -White Box- server platform to Tier 1 (IBM); dramatically increased system reliability, enabled leveraging of Tier 1 competency, and boosted customer adoption.

* Eliminated substantial time and costs associated with development, identifying and negotiating terms with VAR/integrator.

* Increased resolution 100X, directing process development of commercial image sensor.

* Enabled scalability and improved practicality of custom sensors, while saving company +$100K/month, transitioning fabrication to commercial water fabs, and managing all technical and commercial relationships with multiple foundries.

LIGHTWAVE MICROSYSTEMS, (acquired by Neophotonics) San Jose, California * 3/1999 - 10/2002

Manufacturer of passive and active integrated optical components for fiber optic communications.

Director - Manufacturing & Technology

Oversaw and led department comprised of +50 engineers, technicians, and direct labor specializing in wafer fabrication of silicon-based photonic devices. Managed all aspects of process development, integration, yield, sustaining engineering, and equipment maintenance. Held budget authority for all fab capital and expense, as well as personnel budgets. Formulated technology roadmaps. Reported directly to COO.

Achievements:

* Played vital role in creation of best-of-breed planar lightwave circuits, managing all aspects of procurement to build water fab, coordinating with all entities from architects and contractors to city building authorities, making all capital equipment decisions, and formulating adoption of key semiconductor process technologies for optical device fabrication.

* Built high-performance development and production organizations including all processes supporting $1M/week run-rate; consistently delivered products on-time and within budget.

* Maximized communication with internal and external customers, managing integration of design, test, and product groups, participating in corporate strategic planning, and delivering presentations to customers and investors.

dpiX, Palo Alto, California * 7/1997 - 2/1999

Developer and manufacturer of high-resolution flat panel x-ray sensor arrays; f.k.a. Xerox PARC Company.

Manager - Process Engineering

Managed all aspects of process engineering for AMLCD and x-ray sensor array manufacturing, as well as all process module development.

Achievements:

* Improved fab Work in Progress (WIP) management regarding forecasting, creating robust systems.

* Lowered cycle-time by +30% in 9 months, reengineering numerous processes.

* Increased yield by +5% per month, implementing yield monitoring practices for root-cause analysis.

* Streamlined and enhanced development process, introducing -design of experiments- and structured technology reviews.

* Pioneered SPC program including implementation of methodologies for corrective action.

JONATHAN G. BORNSTEIN

* Page 3 *

************@*******.***

CYPRESS SEMICONDUCTOR, San Jose, California * 2/1991 - 7/1997

Designer and manufacturer of multi-product semiconductors.

Integration Manager * 2/1995 - 7/1997

Coordinated and led integration of interconnect architecture scalability, reliability, and process development.

Achievements

* Enabled vertical scaling of interconnect architecture with respect to tradeoffs in yield and device performance for deep submicron technology, designing multiple innovative methodologies.

* Directed model development for stress migration reliability using finite element analysis of thermo-mechanical stress in chips.

* Led development of process architecture and device integration for micro-electromechanical diffractive digital display at company`s wholly owned subsidiary, Silicon Light Machines.

Staff Integration Engineer * 2/1991 - 2/1995

Headed interconnect development of Field Programmable Gate Array (FPGA) program in coordination with corporate partner QuickLogic.

Achievements:

* Single-handedly designed and developed low temperature -Si anti-fuse via formation, multilevel metallization, and associated planarization.

* Served as principal contributor to development of process module for PECVD dielectric films, planarization of pre- and intermetal dielectric levels and spin-on glasses, silicide formation, and variety of multilevel interconnects.

NOTE: Additional experience includes role as Manager - Process Integration & Development, INTEL CORP., PHOTONICS TECHNOLOGY OPERATION (11/2002 - 8/2003). Led process integration group including management of overall development, integration, and yield of technologies for passive and active planar lightwave circuits and hybrid devices prior to operation closure in 10/2003. Details on request.

EDUCATION

Master of Science in Materials Science & Engineering

Stanford University, Stanford, California

Bachelor of Science in Chemistry (American Chemical Society Honors)

Antioch College, Yellow Springs, Ohio

***Full list of 13 US patents available on request***

Contact this candidate