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Resume:

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on Semiconductor Technology for

Ultra Large Scale Integrated Circuits

and Thin Film Transistors (ULSIC vs. TFT)

Editor:

Y. Kuo

Texas A&M University

College Station, Texas, USA

Sponsoring Division:

Electronics and Photonics

Published by TM

The Electrochemical Society

Vol. 22 No. 1

65 South Main Street, Building D

Pennington, NJ 08534-2839, USA

tel 609-***-****

fax 609-***-****

www.electrochem.org

This book has been registered with Copyright Clearance Center.

For further information, please contact the Copyright Clearance Center,

Salem, Massachusetts.

Published by:

The Electrochemical Society

65 South Main Street

Pennington, New Jersey 08534-2839, USA

Telephone 609-***-****

Fax 609-***-****

e-mail: ***@***********.***

Web: www.electrochem.org

ISSN 1938-6737 (online)

ISSN 1938-5862 (print)

ISBN 978-1-56677-736-4 (CD-ROM)

ISBN 978-1-60768-085-7 (PDF)

Printed in the United States of America.

PREFACE

This issue of ECS Transactions includes 33 papers that were presented at the

Second International Conference on Semiconductor Technology for Ultra Large

Integrated Circuits and Thin Film Transistors (ULSIC vs. TFT II), held in the Xi an

Garden Hotel, Xian, China, July 5-10, 2009. This symposium was sponsored by the

Engineering Conferences International.

This conference provided a forum on the latest developments in the two largest

semiconductor industries, i.e., ULSIC and TFT-LCD. Global experts from universities,

industry, and governments exchanged their experience, knowledge, and visions through

technical presentations and discussions during the presentation time, brainstorming

sections, and afternoon and evening breaks. Future scientific and technology challenges

were forecasted and debated. A large number of graduate students from various countries

presented poster papers and were engaged in discussions. Participants were from

Belgium, Canada, China, France, Germany, Hong Kong, India, Japan, Korea, Singapore,

Netherlands, Taiwan, UK, and the USA.

The plenary speeches were dedicated to 1) Technology Development Strategy of

Chinese IC Fabrication by T. Ye of Institute of Microelectronics, Chinese Academy of

Sciences, Beijing, 2) An Overview of NEDO's Electronics Technology Development

Projects by A. Ando of NEDO, Japan, and 3) Reliability and Optimization by W. Kuo of

City University of Hong Kong. In total, 81 papers were scheduled into the following

sections:

Plenary

Modeling, Simulation, and Scaling

Challenges in ULSI Gate Dielectrics

Challenges in Si-based TFT Technology

Challenges in ULSI Substrates and Materials

Challenges in TFT Materials

Challenges in Advanced ULSI Processes

Challenges in Flexible Electronics

Challenges in New Devices and Applications

Challenges in Nano Devices

Posters

The conference also included three panel sessions on 1) Challenges in Devices

and Scaling, 2) Challenges in Materials and Applications, and 3) Challenges in ULSIC

and TFT Fabrications.

In order to present subjects in a coherent manner, papers in this issue of ECS

Transactions have been arranged into six sections. All manuscripts are published as

originally received, without alteration of technical contents.

The success of this conference is contributed by seamless efforts among

conference co-chairs Professors M. Shur, W. Milne, S. Xiong, and D. Ast, who were

iii

involved in coordination, organization, and collaboration of many critical activities. The

local chair Professor C. Liu and committee member Professor S. Wu played important

roles in communicating with central and local Chinese governments and the Xi'an

Jiaotong University as well as offering many valuable advices and services.

The following people are greatly appreciated for various conference activities:

Plenary and invited speakers for their presentations and panel discussions

Session chairs for conducting the meeting

Authors and presenters for their participation

Scientific advisory committee members for their contributions in planning and

coordinating the program

Dr. N. Li for valuable suggestions and serving as the conference ECI liaison

Mr. C.-H. Lin for his administrative supports

ECI staffs for effectively management of the conference

the Staff of the Electrochemical Society for professional work in publishing this

issue of ECS Transactions.

Yue Kuo

Texas A&M University

Acknowledgements

Conference chairs express their sincere thanks to the generous sponsorship of:

Semiconductor Energy Laboratory

Electrochemical Society Electronics and Photonics Division

Conference chairs also thank the valuable technical sponsorship from:

Electrochemical Society Electronics and Photonics Division

Japan Society of Applied Physics

Korean Physical Society Semiconductor Division

MRS-Taiwan

Sematech

IMEC

National Natural Science Foundation of China

Xi'an Jiaotong University

Conference Co-chairs

Yue Kuo, Texas A&M University

Michael Shur, Rensselaer Polytechnic Institute

Dieter Ast, Cornell University

William Milne, Cambridge University

Shaozhen Xiong, Nankai University

Local Committee Chair

Chunliang Liu, Xi'an Jiaotong University

Local Organizing Committee

Shengli Wu, Xi'an Jiaotong University

Jinhai Si, Xi'an Jiaotong University

Zhihu Liang, Xi'an Jiaotong University

Scientific Advisory Committee

G. Bersuker, Sematech S. Higashi, Hiroshima U.

O. Bonnaud, U. de Rennes I H. P. Hsieh, National Chiao Tung U.

I. Boyd, U. College London R. Huang, Peking U.

D. N. Buckley, U. Limerick J. Jang, Kyung Hee U.

G. Celler, Soitec T. P. Ma, Yale U.

T. C. Chen, IBM Watson R0esearch Center J. Murota, Tohoku U.

C. Claeys, IMEC J. Peterson, Albany Nano Tech

S. Fonash, Pennsylvania State U. A. Nathan, U. College London

S. Hamaguchi, Osaka U. R. Street, PARC

M. K. Han, Seoul National U. S. Uchikoga, Toshiba

M. Hatano, Hitachi Y. Yamamoto, Sharp

Session Chairs

G. Bersuker, Sematech J. Murota, Tohoku U.

O. Bonnaud, U. Rennes 1 A. Nathan, U. College London

C. Claeys, IMEC B.-Y. Nguyen, Soitec

K. L. Pey, Nanyang Technological U.

S. Fonash, Pennsylvania State U.

D. Pribat, Ecole Polytechnique, Palaiseau

M. Hatano, Hitachi

J. Stathis, IBM

R. Huang, Peking U.

M. Shur, RPI

R. Ishihara, Delft U. of Technology

F. Templier, CEA-LETI Minatec

J. Jang, Kyung Hee U.

S. Xiong, Nankai U.

Y. Kuo, Texas A&M U.

O. Weber, CEA-LETI

T. P. Ma, Yale U.

C. Wu, Nankai U.

W. Milne, Cambridge U.

ECS Transactions, Volume 22, Issue 1

2009 International Conference on Semiconductor Technology for Ultra Large Scale

Integrated Circuits and Thin Film Transistors (ULSIC vs. TFT)

Table of Contents

Preface iii

Chapter 1

Challenges in ULSI Gate Dielectrics

Nanoscale Gate Stacks: From Atomic Defects to Device Performance * 3

G. Bersuker, C. Park, J. Price, P. Lysaght, P. Kirsch and R. Jammy

Impact of Gate Dielectric Breakdown Induced Microstructural Defects on 11

Transistor Reliability *

X. Li, K. Pey, V. Lo, R. Ranjan, C. Tung and L. Tang

Time-to-Breakdown Behavior and Mechanism on U-grooved n-MOSFET 27

J. Seo, H. Park, G. Kang, J. Kang and B. So

Chapter 2

Challenges in Si-based TFT Technology

TFT Technology Programs in China * 35

S. Xiong, Z. Meng, C. Wu, J. Li, J. He and F. Zhang

From Amorphous-Si Thin-Film-Transistors to Single Crystal-Si Transistors: 49

Influence of Si Crystallinity on Device Properties *

F. Templier

Single Grain Si TFTs for RF and 3D ICs * 57

R. Ishihara, A. Baiano, T. Chen, J. Derakhshandeh, M. D. Tajari Mofrad,

M. Danesh, N. Saputra, J. R. Long and C. I. Beenakker

vii

Chapter 3

Challenges in ULSI Substrates, Materials and Processes

High Scalability and Low Variability of Planar Fully Depleted SOI MOSFETs * 71

O. Weber, F. Andrieu, C. Fenouillet-B ranger, C. Buj-Dufournet, V. Barral,

P. Perreau, L. Tosti, L. Brevard and O. Faynot

Selective Epitaxy of Si and SiGe for Future MOS Devices * 81

I. Mizushima

Substrate Engineering for 32nm and Beyond * 91

B. Nguyen, C. Mazur and G. Celler

Defect Aspects of Ge-on-Si Materials and Devices * 99

C. Claeys, G. Eneman, G. Wang, L. Souriau, R. Loo and E. Simoen

Atomically Controlled Processing for Group IV Semiconductors * 111

J. Murota and M. Sakuraba

Atomic Layer Doping for Future Si Based Devices * 121

B. Tillack and Y. Yamamoto

16kb Phase Change Memory Test Chip with 0.18- m Process 133

S. Ding, Z. Song, B. Liu, D. Cai, X. Chen, Y. Chen, M. Zhong, G. Feng, C. Xu,

S. Feng, Z. Xie, Z. Yang, X. Wan, F. Zhang, G. Wu and Y. Xiang

Dry Etching of Nanosized Si2Sb2Te5 Patterns using TiN Hard Mask for High 145

Density Phase-change Memory

G. Feng, Z. Song, B. Liu, S. Feng and B. Chen

Ultra Thin Oxide by Chemical Vapour Oxidation of Si 151

B. J. Kailath, A. DasGupta and N. DasGupta

Effect of Ge2Sb2Te5 Material Properties on its CMP Process 161

M. Zhong, Z. Song, B. Liu, S. Feng, F. Zhang and Y. Xiang

Atomic Vapor Deposition of TiN with Diluted Tetrakis (diethylamido) Titanium 167

(TDEAT) for Phase Change Memory

L. Wang, B. Liu, Z. Song, S. Feng, Z. Zhou, Y. Xiang and F. Zhang

Surface Roughening and Microstructure of Tantalum Nitride Films Sputtered at 175

Different N2/Ar Flow Ratios

J. J. Yang, B. Liu, Y. Wang and K. W. Xu

viii

Chapter 4

Challenges in Advanced TFT Processes

A-Si:H TFT Nonvolatile Memories and Copper Interconnect for Rigid and 183

Flexible Electronics *

Y. Kuo

Metal induced crystallized poly-Si Thin Films and Thin Film Transistors 191

C. Wu, Z. Meng, S. Zhao, X. Li, Z. Liu, J. Li, M. Wang, H. Kwok and S. Xiong

Stability Study of ZnO TFT using a Simple and Effective Model 201

C. Dong, J. Li, B. Jin, D. Bub and Y. Su

Design of poly-Si TFT Shift Register and Latch Circuit by PMOS Process 207

P. Sun, C. Wu, Z. Meng, Y. Yao, L. Zhao and S. Xiong

Chapter 5

Challenges in Modeling, Simulation, and Scaling

Model and Key Fabrication Technologies for FeRAM * 217

T. Ren, M. Zhang, Z. Jia, L. Wang, C. Wei, K. Xue, Y. Zhang, H. Hu, D. Xie and

L. Liu

Down-scaling of Thin-Film Transistors: Opportunities and Design Challenges 227

X. Guo, R. Sporea, J. Shannon and S. R. Silva

Simulation of SET process in Phase-Change Random Access Memory by Three- 239

Dimension Finite Element Modeling

Y. Gong, Z. Song, Y. Ling, B. Liu, Y. Liu and S. Feng

Three-dimensional Finite Element Analysis of Phase Change Memory Cell with 249

Thin TiO2 Stop Layer used for Forming Deep Sub-micro Electrode

Y. Liu, Z. Song, Y. Ling and S. Feng

Chapter 6

Challenges in New and Nano Devices and Applications

Bipolar Device and Circuit Technologies for Future Wireless Communications * 261

K. Washio, N. Shiramizu, M. Miura, T. Nakamura, K. Oda and T. Masuda

Novel Asymmetric Tunneling Devices for Low Power ULSI * 273

N. Venkatagirish, A. Tura, R. Jhaveri, H. Chang and J. C. Woo

SOI CMOS Platform for Gas Sensing Applications * 281

W. I. Milne, S. Santra, F. Udrea, S. Ali, P. Guha, S. Vieira, S. Maeng and

J. Gardner

Vertical Channel Thin Film Transistor Technology: Similar Approach with 3D- 293

ULSI Monolithic Technology *

O. Bonnaud

Lateral Porous Alumina Templates for Planar Organisation of Carbon Nanotubes 305

and Semiconductor Nanowires *

D. Pribat, M. Gowtham, C. Cojocaru and B. S. Kim

Fabrication and Transport Behavior Investigation of Gate-All-Around Silicon 317

Nanowire Transistor from Top-Down Approach *

R. Huang, R. Wang, Y. Tian, J. Zhuge, L. Zhang, C. Liu, Y. Wang, Y. Ai and

Y. Wang

Breakdown of Small Diameter Si Nanowires under External Electric Field: 327

First-principle Calculation

R. Zhang, N. Gao, Z. Wen and Q. Jiang

Author Index 335

* = invited paper

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