Engineer Design

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SUBODH PRABHU

O BJECTIVE

Seeking challenging and senior opportunities in RTL design, functional verification and systems architecture.

C AREER SUMMARY

Over four years of experience in Verilog RTL design with exposure to complete VLSI flow from architecture to FPGA.

ASIC design and SoC validation in four different generations of mobile multimedia co-processors at STM, India.

Implemented high level synthesis flow using Catapult C and co-sim functional verification environment from scratch.

Have a wide skill set (EDA, S/W) in diverse domains (mobile, imaging, networking, HSSI); cross-cultural exposure.

E DUCATION

MS in Electrical & Computer Engineering, Texas A&M Univ.; 3.82 GPA Aug 08-May 10

Courses : Adv. VLSI Design, VLSI Algorithms; Adv. Computer Arch., Comp. Arithmetic Unit Design; Parallel & Distributed

Algorithms, Algorithm Analysis & Design; Computer Vision, Digital Image, Data Compression, Comp. Human Interface

BE in Electronics & Communications, Delhi Univ./Netaji Subhas Inst of Tech; 80.7% (4.0GPA) Aug 01-Jun 05

Courses : Microelectronics II; Digital Ckts. & Systems II, Comp. Arch., Microprocessors, Signals Systems; DSP II, Linear IC

W ORK EXPERIENCE

Cisco Systems Inc., San Jose, USA HW Engineer II, LAN Switching (Jun 10-Present)

Built a Vera co-sim environment from scratch for Verilog vs C++ testing of a High Speed Switching IP.

Drafting & executing on a CRV based verification strategy in a startup like environment with minimal supervision.

STMicroelectronics Pvt. Ltd., Gr. Noida, India Design Engineer II, Imaging (Aug 05-Jun 08)

Designed a novel 70Kgate/800 MBps bit-stream adaptive JPEG encoder in Verilog for 65nm, 12MPixel CMOS imager

Implemented site-wide High Level Synthesis methodology for generating netlist from C (Catapult) level description.

Interacted with different functional groups across multi-sites to co-ordinate and manage an IP & verif repository system.

Verilog implementations of a host of DSP algorithms for 120-65nm mobile multimedia chips. slant offset correction,

anti-vignette, lens shading, image enhancement, image restoration, GPIO, DMA.

SoC validation for four different chip families. Required working in multi-ethnic, multi-nationality environment.

Center for Electronics Design and Technology, Delhi (Dr. Dobb s Journal), Research Asstt. (Dec 04-Jan 05)

Designed a novel RS232-Ethernet Bridge using ZiLOG eZ80F91 MCU. Remotely monitored UPS of ECE dept.

Quazar Tech, Delhi Summer Intern (May 04-Jun 04)

OMNiSCOPE, a low cost (40USD) Digital Storage Oscilloscope using Intel 8051 with support for industry features.

S ELECT ACADEMIC/RESEARCH PROJECTS

DVFS aware simulator for benchmarking architectural optimizations in NoC (HPCA 10 SAW-1), MS Thesis, Fall 09

Trace cache extension for SimpleScalar Adv. Comp. Arch., Spring 09

Parallel implementation of RANSAC in OpenMP Parallel Algorithms, Spring 09

Negabinary multi-operand adder using column compression techniques Adv. VLSI Design, Fall 08

Panoramic view of Panoramic Computation Comp. Vision, Fall 08

Ethernet based CCD Camera Controller using ZiLOG BE Senior Design, Spring 05

Compiler based Arbitrary Waveform Generator (Circuit Cellar 07), As part of End term project, Fall 04

IR-based Voice Codec using Cypress Programmable SoC Research topic, Fall 03

T OOLS/LANGUAGES SKILL SET

EDA tools: Verilog, VHDL, CatapultC, Specman, OVM, Vera, PSpice, Cadence ncSim, Simvision, HAL, OrCAD,

LEC; Synopsys Design Compiler, Formality; Xilinx ISE, COPS, ChipIt, espresso, SimpleScalar, ocin_tsim (NoC sim).

Software: C++, JAVA, XML, MATLAB, OpenGL, Perl, Tcl/Tk, PHP, SQL, Shell, ASP.NET, VB, VC++, HTML, CSS

Platforms: Unix, Solaris, DOS, OpenMP, MPI; SVN, Synchronicity (RCS), MS Visual Studio; Adobe Framemaker, CS3

A WARDS/ PROFESSIONAL ACHIEVEMENTS

Academics: Graduate Assistantship by OAR, Texas A&M (2009), One-time Scholarship by ECE Dept, Texas

A&M (2008-2009), Merit Scholar by NSIT (2001-05), Indira Zonal Top Scorer Award by Govt. Delhi ( 99, 01).

Career: Promoted ahead of turn to Design Engineer II designation at STM for my proactive approach.

Contests: III place in Microsoft College Puzzle Challenge 2009, Distinctive Excellence Award in ZiLOG 2004 Flash

Nets Cash Contest, Special Prize in Original HW Design & numerous college level prizes for various digital H/W designs.

Teaching: Certified trainer for Computer Basics by STFoundation at 4 sites in India & US; Taught Embedded Systems

at JSS, Noida & CMC, Delhi; Conducted Programming AVR workshop at CEDT Lab, NSIT.

Posts: ISMA/GSC Mentor at TAMU; Gen Secy at IEEE NSIT Student Branch; organized various workshops/symposia.

US work authorization: H-1B (01OCT10-01JUL13) LUO: 21JUL11

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