Power Energy
Resume:
Reducing Energy in FPGA Multipliers Through Glitch
Reduction
Nathaniel Rollins and Michael J. Wirthlin,
****@**.***.***, and ********@**.***.***
Department of Electrical and Computer Engineering
Brigham Young University, Provo, UT. 84602
Abstract larger loading than custom circuits. The signal
bu ers, pass transistors and other programmable
switching structures signi cantly increase the capac-
While FPGAs provide exibility for performing high-
itive load of signal nets over dedicated metal wires.
performance DSP functions, they consume a signif-
This loading burden increases both the delay of in-
icant amount of power. For arithmetic circuits, a
terconnect as well as the power. Several studies sug-
large portion of the dynamic power is wasted on un-
gest that the primary contribution in global system
productive signal glitches. Pipelining can be used to
timing is the global interconnect [2]. It has also been
signi cantly reduce the unproductive power wasted
shown that most of the power dissipated by an FPGA
in signal glitches. This paper presents a methodol-
design occurs in the interconnect[3].
ogy for estimating the amount of power consumed
by glitches and applies this methodology to non-
Because of the relatively large capacitive loading
pipelined, pipelined, and digit-serial multipliers. This
of programmable interconnect, the switching activity
glitch estimation is used to evaluate these multipliers
of individual signal wires will have a signi cant con-
using four energy metrics: energy per operation, en-
tribution to the dynamic power of the circuit. Much
ergy delay, energy throughput, and energy density.
of the dynamic switching power can be wasted in un-
Understanding the energy cost of arithmetic opera-
productive circuit glitches . Signal glitching refers
tors can be used to aid the designer or synthesis tool
to the transitory switching activity within a circuit
in the creation of energy e cient datapath circuits.
as logic values propagate through multiple levels of
combinational logic. While glitching is not unique to
FPGAs, the relatively high capacitive loading of pro-
1 Introduction grammable interconnect places a much higher power
cost to signal glitching for FPGAs. Previous studies
have shown that power dissipation caused by glitch-
The exibility, reprogrammability, and high per-
ing can makeup a signi cant amount of total dissi-
formance of eld programmable gate arrays (FP-
pated power[4, 5].
GAs) make them an attractive architecture choice
for many digital signal processing (DSP) applica-
An important technique for reducing FPGA power
tions. FPGA designs however, consume more power
consumption is to reduce the amount of signal glitch-
than application-speci c integrated circuits (ASICs)
ing within the circuit. Pipelining is one technique
[1] which makes them less attractive for wireless and
for reducing signal glitches. Previous studies have
handheld DSP applications. Consequently, energy
shown that pipelining can be used to reduce power
consumption is becoming a critical design parameter
by 90% [6]. A pipelined design has less logic be-
for high-performance signal processing applications.
tween registers and therefore is less prone to glitch-
Designers must increasingly consider the impact of
ing. Pipelining an FPGA design can come at lit-
power on FPGA signal processing systems.
tle or no cost since ip- ops are included in every
The programmable nature of FPGA interconnect FPGA logic block and often go unused. Digit serial
results in an interconnect structure with signi cantly techniques, a form of pipelining, can also be used to
reduce signal glitching in arithmetic circuits [7]. signal transitions on interconnect lines caused by
unequal logic or interconnect delays. For example
This paper will describe a methodology for es-
consider the signal activity of an N-bit ripple carry
timating the power associated with glitches within
adder. When new inputs arrive at the adder, all N-
FPGA datapath circuits. This paper will quantify
bit sums are computed simultaneously but the carry
the dynamic glitch power, energy per operation, en-
bits must ripple from the least signi cant bit up to
ergy delay, energy throughput, and energy density of
the most signi cant bit. The most signi cant bit of
each multiplier used in the study. This methodology
the adder could switch N times due to this rippling.
will be applied to a wide variety of multiplier circuits
Only the nal transition can be called a productive
including non-pipelined multipliers, pipelined multi-
transition and so any other transitions are called
pliers (with various pipelining levels), and digit-serial
glitches. The carry-out of the 32nd bit of a 32-bit
multipliers. The methodology presented and results
carry chain will have on average 2x more useless tran-
from the study can be used by designers and high-
sitions (glitches) than useful transitions per cycle and
level synthesis tools to properly select arithmetic op-
the sum output will have on average 1.5x more use-
erators based on energy consumption.
less transitions per cycle[9]. Fast carry chains in FP-
GAs may signi cantly reduce the glitching caused by
This paper will begin by describing the impor-
such an example, however FPGA designs are laden
tance of dynamic transient power in FPGA circuits.
with glitches caused unequal line lengths leading to
A methodology will be described for carefully es-
combinational logic block (CLB) logic.
timating the static, dynamic, and glitch dynamic
power of datapath circuits. This methodology will Estimating the glitches that occur in FPGA de-
be applied to a combinational multiplier to identify signs is important in order to understand how much
the unproductive glitching power component. Next, power is consumed by glitching. A static simulator
the energy measures used to evaluate power will be cannot estimate dynamic signal activity and thus is
introduced. These will include energy per operation, not su cient for accurate glitching power analysis of
energy delay, and energy density. The paper will ap- an FPGA design. A previous study demonstrated
ply this methodology to a number of non-pipelined how static simulations of FPGA circuits can under
multiplier circuits and highlight the signi cant con- estimate the circuit signal activity. In that study,
tribution of glitches in circuit power. The paper will the dynamic power estimation was 24% less than the
continue by applying this methodology on pipelined actual power consumption [4]. In designs with larger
circuits and digit-serial circuits. These circuit types amounts of glitching (such as a multiplier) the accu-
will be compared by evaluating the operation en- racy of such a static power model will be even worse.
ergy of each implementation style.
An accurate power estimation should take sig-
nal glitching into account. To produce an e ective
power estimation, a back-annotated timing model is
2 Dynamic Transient Power required in order to quantify net delays. A timing
simulation which uses this back annotated timing
Dynamic power makes up a large portion of the to- model will then be able to simulate glitches so that
tal amount of power consumed by an FPGA de- the amount of glitching can be determined. A power
sign. FPGA interconnect is largely responsible for analysis based on this timing simulation will produce
dynamic power consumption. It has been shown that a more accurate power consumption estimation.
the interconnect of an FPGA accounts for the major-
ModelSim together with Xilinx s ISE tools can be
ity of the area on an FPGA chip and also accounts
used e ectively to model dynamic transient signal ac-
for the majority of the power dissipated by FPGA
tivity and produce an accurate power consumption
designs[8]. The amount of power consumed by the
estimation. The Xilinx tools can be used to gener-
interconnect and clock tree can account for up to
ate a back-annotated timing le which can be used
86% of total dissipated power[8]. Unnecessary and
by ModelSim to e ectively model glitching through a
unproductive use of FPGA interconnect will there-
timing simulation. The amount of glitching reported
fore be very costly in terms of power.
by ModelSim depends on the granularity chosen for
Unproductive interconnect activity is usually the simulations. This study nds that a resolution of
caused by glitching. Glitching refers to spurious 100ps is su cient. ModelSim simulations can be cap-
2
tured and recorded in a le which reports the switch- delays and varied net lengths which lead to a large
ing activity of every net in a design. The switching number of glitches[8, 11]. The multiplier in Figure
activity of each net can be analyzed and tabulated 1 shows that pipelining can be easily implemented
into two categories: unproductive glitching transi- by adding registers between multiplier stages. Addi-
tions and productive signal transitions. Power esti- tionally, a digit-serial multiplier based on the repre-
mation tools such as XPower[10] can then use this sentation in Figure 1 can be easily created[7, 12]. A
report to estimate the power consumption of the de- pipelined multiplier and a digit-serial multiplier are
sign. used in later sections to show how glitches can be
reduced in order to lower the operation energy.
The overall power consumption of a single circuit
component can be broken into three categories: nor- 4x4 Multiplier X
malized static power, dynamic glitching power and 4
Y0
the remaining dynamic power. Mult Stage
5
Y1
Mult Stage
Static Power The static power of an individual cir-
cuit module is obtained by dividing the total 5
Y2
static power of the device by the relative size of Mult Stage
the circuit (i.e. # Circuit LUTs / Total LUTs). 5
Y3
For circuits such as multipliers with large signal Mult Stage
activity, this component is relatively small.
Dynamic Glitching Power The glitching power
P7 P6 P5 P4 P3 P2 P1 P0
is obtained by counting the temporary signal
glitches in the timing simulation. The percent-
Figure 1: 4x4 multiplier.
age of signal glitches to total glitches is used
to divide the dynamic power between glitching
power and useful dynamic power. For a non-pipelined multiplier the amount of
Useful Dynamic Power The useful dynamic glitching increases super-linearly as the size of the
power is obtained by tabulating the useful multiplier grows. To show this behaviour power esti-
transitions within the module. If the nal value mates are performed on 4x4, 8x8, 16x16, and 32x32
of a signal is di erent from the beginning of a multipliers. Random inputs are presented at the in-
clock cycle to the end, then a useful transition puts for all simulations. The pie charts in Figure 2
is the last transition that occurs, and all others show the breakdown of the total power into its con-
are glitches. Otherwise, all transitions during stituent parts of static power, dynamic glitch power
the clock cycle were glitches. and remaining dynamic power. For all four multiplier
sizes the amount of static power used by the design
This study will show that the dynamic glitching makes up less than 1% of the total power. Note how
power and the remaining dynamic power make up the percentage of dynamic glitch power increases as
the majority of the total power for arithmetic cir- the bitwidth of the multiplier grows. In the case of
cuits such as multipliers. Reducing one or both of the 4x4 multiplier glitching accounts for about 12%
these parts is the key to reducing overall power con- of the total power. As the multiplier grows to a 32x32
sumption. multiplier, the total power is dominated by glitching
which accounts for 76% of the total power.
3 Multiplier Dynamic Glitch
4 Reducing Glitch Power
Power
Through Pipelining
This study uses multiplier designs to demonstrate the
e ects of glitching on total power consumption and Pipelining a design is an intuitive way to reduce
on operation energy. A multiplier is a good design glitching. A pipelined circuit has less glitching due to
to demonstrate this due to it s large amount of net the reduced amount of logic between registers. With
3
4-bit 8-bit 16-bit 32-bit
12.5% 0.2% 0.2% 0.1% 0.0%
24.1%
31.7% STATIC POWER
46.6% DYNAMIC POWER
53.2%
DYNAMIC GLITCH
68.2% POWER
75.9%
87.3%
Figure 2: Breakdown of power constituents for a multiplier of various bitwidths.
less logic between registers, the amount of intercon- Glitching as a Percentage of Total Transitions
nect between registers is also reduced. Pipelining
100
also causes long routing interconnect to be broken 90
up by registers resulting in a smaller range of logic 80
70
and interconnect delays. Consequently less glitch- 4-bit
60
ing occurs. In many cases pipelining can be imple- 8-bit
50
16-bit
mented with little additional cost since often many 40
32-bit
30
of the ip ops within the design s CLBs go unused. 20
When pipelining can be used to reduce glitching, the 10
0
amount of power consumed by a design is also re-
0 1 2 4 8 16 32
duced. Number of Pipeline Stages
Implementing pipelining on the multiplier design
previously presented shows how fewer glitches re- Figure 3: The amount of glitching as a percentage
duces overall power consumption and operation en- of total design transitions for multipliers of various
ergy. Pipeline stages are strategically inserted in the widths and varying amounts of pipelining.
multipliers of di erent bitwidths (4x4, 8x8, 16x16,
and 32x32). For each multiplier, pipelining is grad-
ually introduced until the multiplier is completely
dicates that as pipelining begins to be applied to the
pipelined.
multiplier there is a large initial pay-o in reduc-
Figure 3 shows how glitching is reduced as pipeline tion of power due to glitching. After a certain point
stages are inserted. The graph reports the number there is less power savings to be had by increasing
of glitches as a percentage of the total signal tran- the amount of pipelining.
sitions for each multiplier. The glitching percentage
drops with the amount of pipelining introduced. The
5 Reducing Glitch Power
almost linear quality of the graph indicates that the
advantages gained from pipelining pay o right up
Through Digit-Serial Com-
until the multiplier is fully pipelined.
putation
As the amount of glitching goes down the amount
of power consumed due to glitching is also reduced.
Figure 4 shows how the dynamic glitching power low- Pipelining the stages of a multiplier has proven to
ers as the amount of pipelining increases. This log- be an e ective way of reducing glitching (see Fig-
arithmic graph agrees with the intuition that as the ure 3). The amount of pipelining available in the
amount of glitching goes down (see Figure 3) the multiplier shown in Figure 1 is limited by number
amount of power consumption due to glitching also of multiplier stages. In other words an NxN multi-
goes down. The logarithmic quality of the graph in- plier can have a maximum of N pipeline stages. The
4
Total Energy
Dynamic Glitching Power as a Percentage of Total Power
1000
80
70
60 4-bit
100
4-bit
50 8-bit
8-bit
(nJ)
16-bit
40
16-bit 32-bit
30 10
32-bit bit-serial
20
10
0 1
0 1 2 4 *-**-**-*-*-*-*-*-** 32
Number of Pipeline Stages
Number of Pipeline Stages
Figure 5: Total energy consumption (in nJ/cycle) of
Figure 4: The amount of dynamic glitching power as
a multiplier of di erent widths and various amounts
a percentage of total power for multipliers of various
of pipelining compared to the total power consump-
widths and a varying amount of pipelining.
tion of a bit-serial multiplier with operands of di er-
ent widths.
graph in Figure 3 suggests that glitching could be fur-
ther reduced if additional pipelining was available.
Additional pipelining is available in a digit-serial tiplier based on the design of Figure 1 is one product
multiplier where pipelining is applied at a smaller per cycle, the throughput of a bit-serial multiplier
granularity[12]. A bit-serial multiplier is pipelined at is one product per N*2 cycles. New operands are
the bit level. It can reduce the amount of glitching to introduced to a bit-serial multiplier every N*2 cy-
less than 1% of total signal transitions (for operands cles. Since the throughput of a design directly a ects
of any width). When compared to the percentages operation energy, even though a bit-serial multiplier
shown in Figure 4 for the pipelined multiplier, the consumes less overall power it may have a larger op-
less than 1% glitching achieved by the bit-serial mul- eration energy than a pipelined multiplier.
tiplier is very impressive. With almost zero glitches,
the amount of power consumed by glitching in a bit-
serial multiplier approaches zero. This means that
at least 98% of the consumed power is due to useful
6 Operation Energy
dynamic power.
Figure 5 compares the overall energy consumption
Most studies quantifying the power consumption of
of the pipelined multipliers with that of the bit-serial
FPGA circuits report on the average power of the
multiplier. The total amount of energy consumed by
overall circuit. For high-throughput arithmetic cir-
the bit-serial multiplier is almost independent of the
cuits, however, the primary concern is the amount of
bitwidth of its operands. For this reason, the total
energy required to perform a speci c arithmetic op-
energy consumption of the bit-serial multiplier for
eration. Understanding the energy consumption of
any width is shown as a single line. The graph shows
individual datapath operators will allow the designer
that a bit-serial multiplier with 32-bit operands con-
or synthesis tool to choose operators that meet a spe-
sumes the same amount of total power as a fully
ci c throughput constraint while minimizing energy
pipelined 4x4 multiplier or 6x less overall power than
consumption.
a fully pipelined 32x32 multiplier.
With such an extreme amount of pipelining the This study will use the glitch estimation technique
minimum clock period of the bit-serial multiplier is presented in the previous section to estimate the
reduced allowing for a faster clock rate. Unfortu- amount of energy consumed by a number of multi-
nately however, the pipelining in a bit-serial unit not plier operators. Four energy parameters will be used:
only increases the latency but also the throughput of energy per operation, energy delay, energy through-
the design. Whereas the throughput of an NxN mul- put, and energy density.
5
6.1 Energy per Operation operation is Eop = P tclk n where n is the number
of clock cycles required to perform the operation.
Energy per operation quanti es the amount of energy
Pipelined operators overlap the computation of
required to complete a single operation of a speci c
several discrete operations in a single clock cycle.
circuit operator. This measure, reported as nJ, is
The energy consumed by a pipelined operator is
more useful than an average power measure when
shared among the various instances of the operator
comparing arithmetic circuits with di erent imple-
in the pipeline. Thus for pipelined operators, rather
mentation approaches. Speci cally, this measure al-
than considering the number of cycles required to
lows us to compare the energy e ciency of multi-
perform the operation (n), the interval between suc-
cycle operators with single-cycle operators.
cessive initiations of the pipeline operation is con-
sidered . The energy for a single computation is
Circuit energy can be computed by integrating the
computed as Eop = P tclk . For = 1 (which is
circuit power consumption over time (E = P dt).
the case for the pipelined multipliers), the operator
Assuming constant power consumption, the energy
is fully pipelined (i.e. a new operation can be initi-
can be estimated by multiplying the average power
ated every clock cycle) and the energy per operation
of the circuit operator by the amount of time to
is Eop = P tclk .
complete a single operation. For single-cycle oper-
ators, the energy per operation is simply the aver-
The bit-serial multiplier is an example of a circuit
age power of the circuit times the clock period, or
with multi-cycle operation. The bit-serial multiplier
Ecycle = P tclk .
does not have a = 1 like the pipelined multipliers,
but has = N 2; where N is the bitwidth of the
The pipelined multiplier is an example of a circuit
bit-serial multiplier operands. Thus, despite its much
with a single-cycle operation. The energy per opera-
lower overall power consumption (Figure 5) in gen-
tion for the pipelined multipliers is shown in Figure 6.
eral the bit-serial multiplier has a large energy per
Energy per operation is a ected by glitching power.
operation.
Just as the graph of power consumption in Figure 4
drops logarithmically, Figure 6 shows that energy per
operation also drops logarithmically. The graph also Energy per Operation
shows that as the width of the multiplier increases, 16-bit 32-bit
16-bit (bit-serial) 32-bit (bit-serial)
energy per operation grows exponentially. 1000
Energy per Operation
100
(nJ)
1000
10
100
4-bit
(nJ)
1
8-bit
10 0 1 2 4 8 16 32
16-bit
Number of Pipeline Stages
32-bit
1
0 1 2 4 8 16 32
Figure 7: Energy per operation (in nJ) of a multiplier
Number of Pipeline Stages
of di erent widths and various amounts of pipelining
compared to the energy delay of a bit-serial multiplier
with operands of di erent widths.
Figure 6: The energy per operation (in nJ) for a
multiplier of di erent widths and various amounts of
The energy per operation of the bit-serial multi-
pipelining.
plier is compared to the pipelined multipliers in Fig-
ure 7 (16-bit and 32-bit operands only). The x-axis of
The energy per operation of multi-cycle circuit op- the graph is irrelevant to the bit-serial plots since the
erators must take into consideration the number of bit-serial multiplier cannot be pipelined any further.
clock cycles required to perform the operation. For For this reason the bit-serial energy per operation
a non-pipelined multi-cycle operator, the energy per plots show up as horizontal lines. The graph shows
6
that the energy per operation of the bit-serial multi- Energy Delay
plier is always greater than the pipelined multiplier 100000
except for one case of the 32x32 pipelined multiplier.
This one case occurs when the 32x32 multiplier is 10000
non-pipelined. Having to take into consideration 4-bit
1000
(nJ ns)
8-bit
causes the large energy per operation for the bit- 16-bit
serial multiplier. For 32-bit operands, the bit-serial 100
32-bit
multiplier requires = 64. Notice the similarity of 10
the graphs in Figure 5 and Figure 7. The value of
1
the bit-serial line in Figure 5 (in nJ) is multiplied 0 1 2 4 8 16 32
by 32 in Figure 5 for the 16-bit operand bit-serial Number of Pipeline Stages
multiplier and by 64 for the 32-bit operand bit-serial
multiplier. In general the energy per operation of
a bit-serial multiplier is lower than the energy per Figure 8: Energy delay (in nJ ns) for a multiplier of
operation of a pipelined multiplier. di erent widths and various amounts of pipelining.
6.2 Energy Delay
serial multiplier consumes almost no energy due to
Energy delay is a related measure that combines the
glitching, but relative to the pipelined multipliers re-
energy e ciency and speed of an operator into a sin-
quires a large number of cycles to complete an op-
gle parameter [13]. This measure is frequently used
eration. The graphs in Figure 9 compares the en-
to balance the trade-o between reducing energy and
ergy density of the bit-serial multiplier with 16-bit
increasing circuit speed. The energy delay of a circuit
and 32-bit operands (where n = 32 and n = 64 re-
operator is computed as Edelay = Ecycle, where
spectively) with the pipelined multipliers (where n =
is the latency of a single computation of the operator.
pipeline depth). Due to the large amount of glitching
The latency of the operation is = tmin n where n
in the 32-bit pipelined multiplier, the bit-serial mul-
is the number of clock cycles required to complete a
tiplier has a lower energy delay. As the size of the
single operation and tmin is the minimum clock time
pipelined multiplier goes down, the energy delay of
period of the circuit.
the pipelined multipliers goes lower than the energy
delay of the bit-serial multiplier.
The minimum clock time period of a circuit de-
creases as the amount of pipelining increases. This
smaller clock period provides greater throughput
for designs with single-cycle operations such as the Energy Delay
pipelined multipliers. However, as we increase the 16-bit 32-bit 16-bit (bit-serial) 32-bit (bit-serial)
amount of pipelining the latency increases (n in-
100000
creases), potentially increasing the energy delay.
Thus, as pipelining is increased the energy delay 10000
could increase due to an increased latency, but the 1000
(nJ ns)
energy delay could also be reduced due the the re- 100
duced amount of glitching.
10
Figure 8 shows how an increased amount of 1
pipelining could either decrease or increase energy 0 1 2 4 8 16 32
delay. In designs which have a large percentage of Number of Pipeline Stages
glitching (see Figure 2) such as the 32-bit multiplier,
increasing the amount of pipelining decreases the en-
Figure 9: Energy delay (in nJ ns) of a multiplier of
ergy delay. In designs with less glitching, energy de-
di erent widths and various amounts of pipelining
lay rises as pipelining is increased.
compared to the energy delay of a bit-serial multiplier
The trade-o of larger latency for less glitching
with operands of di erent widths.
is accented with the bit-serial multiplier. The bit-
7
6.3 Energy Throughput Energy Throughput
100000
The energy throughput parameter is similar to en-
ergy delay in that it combines energy e ciency 10000
and circuit speed into a single parameter. Energy 4-bit
1000
(nJ ns)
8-bit
throughput di ers from energy delay in that it does 16-bit
100
not take into account the number of clock cycles 32-bit
needed to complete a single operation (n), but rather 10
it considers the number of clock cycles between suc- 1
cessive operation initiations . In most cases only 0 1 2 4 8 16 32
one or the other is used. Energy throughput is cal- Number of Pipeline Stages
culated as Ethput = Ecycle tmin, where tmin is the
minimum clock time period of the circuit and is the
interval between successive initiations of the pipeline Figure 10: Energy throughput (in nJ ns) for a mul-
operation. tiplier of di erent widths and various amounts of
pipelining.
Sometimes it is more useful to consider through-
put energy rather than energy delay. In some designs
a pipelined operation is used successively in such a delay of the bit-serial multiplier with the pipelined
way that a new operation can be initiated on each multipliers (16x16 and 32x32 only). It shows that
clock cycle ( = 1). In these cases, energy through- in most cases the energy throughput of the bit-serial
put might be a more desirable parameter than energy multiplier is larger than the energy throughput of the
delay. Energy delay is more useful for designs which pipelined multipliers.
require an operation to complete before a new one
can be initiated ( = pipedepth). Energy Throughput
Where increasing pipeline depth raises energy de- 16-bit 32-bit
16-bit (bit-serial) 32-bit (bit-serial)
lay (due to an increased latency), it lowers energy 100000
throughput. Pipelining bene ts energy throughput 10000
in two ways: it reduces glitches which lowers over-
all energy consumption, and it reduces the minimum 1000
(nJ ns)
clock period - providing a greater throughput. Fig- 100
ure 10 shows how pipelining greatly bene ts energy 10
throughput. Energy throughput (in nJ ns) is dis-
1
played on a logarithmic scale therefore over a range 0 1 2 4 8 16 32
of di erent pipeline depths it appears linear. The Number of Pipeline Stages
graph shows how critical the rst stages of pipelin-
ing are. Implementing only a single pipeline stage in
the 32x32 multiplier reduces the energy throughput Figure 11: Energy throughput (in nJ ns) of a mul-
by an order of magnitude. tiplier of di erent widths and various amounts of
pipelining compared to the energy delay of a bit-
Energy throughput for the bit-serial multiplier is
serial multiplier with operands of di erent widths.
the same as energy density since n = = N 2 where
N is the size of the bit-serial multiplier operands.
Despite its low power consumption (see Figure 5)
6.4 Energy Density
the bit-serial multiplier tends to have a large energy
throughput and energy delay. The bit-serial multi-
plier bene ts from having almost no glitching and The nal energy parameter used in this study is en-
a smaller clock period than the pipelined multipli- ergy density, Edensity . This parameter normalizes
ers. However, it su ers from having a large value. the amount of energy required to perform a single
In almost every case, this large value outweighs operation to the number of logic resources used by
the advantages of a low minimum clock period and the circuit. This parameter can be calculated as
minimized glitching. Figure 11 compares the energy Edensity = Ecycle /A, where A is the area of the
8
circuit. It is important to note that the amount of ergy delay is often lower than the energy delay of
dynamic energy consumed by a circuit module is not the pipelined multipliers. Whereas the area of the
necessarily linearly related to the size of the circuit. pipelined multipliers has no direct correlation with
As described earlier, the primary contributer to dy- its energy density, the energy density of the bit-
namic power is signal glitches. Since circuit size af- serial multiplier is inversely proportional to its area.
fects energy density, large circuits that reduce glitch- The bit-serial multiplier with 4-bit operands has the
ing through pipelining may have a lower energy den- smallest area and the highest energy density. Con-
sity than smaller pipelined circuits. versely, the bit-serial multiplier with 32-bit operands
has the largest area and the smallest energy density.
Figure 12 shows the energy density for the
pipelined multipliers. From the graphs in this g- Energy Density
ure it may appear that energy density is not di- 16-bit 32-bit
rectly related to circuit size, but multiplier size does 16-bit (bit-serial) 32-bit (bit-serial)
1000
impact energy density through average net activity
rate. The 4x4 multiplier has the smallest area but
the largest energy density. The 32-bit multiplier has 100
(pJ/LUT)
very high energy density when it is non-pipelined,
however as pipelining is introduced the energy den- 10
sity drops until it reports the lowest energy density.
1
The energy trends shown in Figure 12 are the re- 0 1 2 4 8 16 32
sult of glitching and average net activity rate. As Number of Pipeline Cycles
expected, glitching is reduced as pipelining is intro-
duced, lowering the overall energy consumption. The
32-bit multiplier demonstrates this trend. However, Figure 13: Energy density (in pJ/LUT) of a mul-
the size of the multiplier also a ects the energy den- tiplier of di erent widths and various amounts of
sity. The nets of a smaller multiplier have a higher pipelining compared to the energy delay of a bit-
average activity rate than a larger multiplier, result- serial multiplier with operands of di erent widths.
ing in larger energy densities for smaller multipliers.
Energy Density
7 Conclusion
1000
This paper presents a methodology for estimating
the glitches of FPGA circuits and uses this method-
100 4-bit
(pJ/LUT)
ology to determine the amount of power wasted in
8-bit
16-bit
glitching. This paper shows that the majority of
32-bit
10
dynamic power in non-pipelined multipliers is con-
sumed by glitches. The glitch power can be reduced
by pipelining the circuit. Results in the paper show
1
0 1 2 4 8 16 32
an exponential decrease in glitch power by increasing
Number of Pipeline Stages
the pipelining depth.
Several energy related measures were introduced
and used to provide better tools for comparing
Figure 12: Energy density (in pJ/LUT) for a mul-
the energy requirements of di erent implementa-
tiplier of di erent widths and various amounts of
tion approaches. Single cycle and multi-cycle cir-
pipelining.
cuit implementations can be compared by estimat-
The graph in Figure 13 compares the energy den- ing the energy per operation rather than the aver-
sity of the bit-serial multiplier with that of the age power consumption. This paper demonstrates
pipelined multiplier (16x16 and 32x32 only). The that while multi-cycle bit-serial operators have signif-
graphs in this gure show that despite being a cir- icantly lower average power, the energy per operation
cuit with a multi-cycle operation, the bit-serial en- is higher than deeply pipelined parallel approaches.
9
Energy delay, energy throughput and energy den- Design of Intergerated Circuits and Systems,
sity were also used to compare the multiplier im- 18(8):1114 1131, August 1999.
plementation approaches. Energy delay is used to
[6] Steven J.E. Wilton, Su-Shin Ang, and Wayne
balance the trade-o between energy reduction and
Luk. The impact of pipelining on energy per
operator latency. Increasing the pipelining depth ex-
operation in eld-programmable gate arrays.
ponentially reduces glitch power, but also increases
In Field-Programmable Logic and Applications.
latency. The amount of pipelining which produces
Proceedings of the 13th International Workshop,
the best trade-o depends on the bitwidth of the
FPL 2004, Lecture Notes in Computer Science,
multiplier. In general, as the bitwidth increases, the
LNCS 3203, pages 719 728. Springer-Verlag,
amount of pipelining producing the lowest energy de-
August 2004.
lay also increases.
[7] Yun-Nan Chang, Janardhan H. Satyanarayana,
The metrics and estimates generated in this paper
and Keshab K. Parhi. Systematic design of
will be used as part of a high-level datapath synthesis
high-speed and low-power digit-serial multipli-
tool. This tool will use energy estimates of the var-
ers. 45(12):1585 1596, December 1998.
ious multiplier implementation approaches to select
the proper multiplication approach. High-power low- [8] Eric Kusse and Jan Rabaey. Low-energy embed-
pipelined circuits will be selected for datapath cir- ded FPGA structures. In International Sym-
cuits with tight latency constraints while low-power, posium on Low Power Electronics and Design
highly pipelined circuits will be selected for latency 1998, pages 155 160, August 1998.
tolerant datapath circuits.
[9] Jeroen Leijten, Jef van Meerbergen, and Jochen
Jess. Analysis and reduction of glitches in
synchronous networks. In European Design
References
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