Design Engineer
Resume:
Title:Software Engineer
**************@*******.***
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Source below
NAME: rancourt, claud
ADDRESS:
ADDRESS2:
CITY: San Jose
STATE: AR
ZIP: 95134
CANDIDATE ID: 2295326
US CITIZENSHIP:
EDUCATION:
EXPERIENCE:
WILL RELOCATE: -
JOB WANTED:
RATE NEEDED:
TELEPHONE:
EMAIL: **************@*******.***
HOMEPAGE:
HOTTEST SKILLS: 2167, 3270, 80.86, a+ certification, abap, active server, activex,
animation, apache, applet, as 400, as/400, as400, assembly language, athlon, autocad,
automatic test equipment, aviation, baan, banyan
REVISION: 22-MAY-02
YOE:
RESUME:
Claude P. Rancourt
13556 Trenton Street, Apt. 101
San Jose, CA 95134
EDUCATION:
1978
- 1980 Olhone College, Fremont, CA Degree ASEE, AC/DC Elec.,
Engineering Constructs, Digital High Speed Design and Calculus
Additional Skills/Training
1993 Specctra Quest, (Formerly CCT)
1995 Cadence Concept
1996 Viewdraw
1996 SMT Technology, Copper Connection, CA
1997 Cadence IC/ASIC & Layout Editor Cadence
1997 IC Layout, Dracula
1998 Protel, PCB
1998 IC Craftsman, Cadence
Objective:
To secure a position which would tax my PCB design and CAD tool knowledge.
1982
to 1987Nokia, Petaluma, CA
Printed Circuit Board Designer
Design and layout of high-density multi-layer boards, high voltage power supplies, relay
panels and fiber optics. Trained drafters and PCB designers on Telesis (Now Allegro)
Maintained computers and Cad programs.
01/87
to 12/87 (Contract) Scantronics, Stockton, CA.
Sr. Designer
Designed boards and redesigned existing layouts many of which were done on high-density
single-sided boards to keep cost to a minimum. All designs done on Allegro
01/88
- 10/91Analog Devices, Norwood MA
Sr. PCB Layout Engineer
Designer of Fine Pitch Surface Mount, Thru-Hole, High Speed, Differential Pair, Impedance
Controlled, ASIC C.O.B. and 8 - 12 Layer Electronic Circuit Boards.
Also Designed Detailed Cable, Component, Assembly, Packaging PCB Strip Fabrication and
Schematic drawings.
Engineered projects:
High Voltage Isolation Signal Modules. Layer restrictive
DUT, ( Device Under Test) modules for testing analog components.
Coordinated and mediated circuit board production between Engineering, Purchasing,
Marketing, Manufacturing, Test Department and Sub-contractors.
11/91
to 12/92Harbor Electronics, Santa Clara, CA.
Senior PCB Design
PCB Design of a wide variety of products including ATE load-boards, probe cards,
evaluation boards, burn-in and cable-off boards. Input process and design database setup.
Library parts creation and checking. Netlists generation, schematic/ design layout, and
proper Eco documentation to accomplish job. Familiarity with board design rules, impedance
control, length matching, power decoupling, cross talk, SMT, analog/digital design, and RF
design. Generating Gerber files and check plots for customer approval. Interfacing with
customers and incorporating changes to a design.
Currently supporting Intel Corp. and National Semi.
01/93
02/94Allied Telesyn Intl., Sunnyvale, CA
Sr. PCB Designer
Designing multi-layer boards for hubs, transceivers, switches and Ethernet adapter cards.
Deals with engineers on their needs for the design and incorporate ECO'S on existing
designs.
03/94
- 12/94Celestica Corporation, Santa Clara, CA
Sr. PCB Designer
Responsible in designing Logic boards with mixed digital and analog signals and follows
customer requirements and specifications using Allegro. Interface with customers to
discuss design changes and the impact on cost and schedules.
01/95
04/95Motorola Pan American Paging Group, Boynton Beach, FL
PCB Designer using Cadence Allegro
Design multi-layer PC boards, surface mount technology. Products are Motorola
Pagers. Update schematics with CONCEPT schematic capture.
05/95
06/96Stratus Computers, Marlborough, MA
PCB Designer using Cadence Allegro for PCB design and Concept to generate schematics.
Boards are large multi-layer, SMT on one or both sides. High-speed layout techniques
applied. Extensive use of the CCT router.
06/96
08/97TRW, El Segundo, CA
Using Allegro performed Electro (PCB design, assembly drawings, mechanical details, cable
drawings) mechanical design. Also used HP-ME10 to design micro-electronic circuits.
Responsible for incorporating ECNs and creating wiring diagrams.
09/97
11/98Gardner Communications, San Jose
Position: Electro-Mechanical Design / Draftsman
Design enclosures and PC Boards for Commercial and Home Satellite Video Communication
Equipment. Package controls and generate required mounting hardware.
12/98
11/99Cisco, San Jose, CA
PCB Designer of eight to twelve layer main- frame boards (auto-routed)
Created and checked net-lists to film to prove program outputs. Many were echo logic
PCB's
.
01/00
01/01Intel Corporation, Hillsboro, OR
Design of multi-layer preeminent Mother boards for future computer products.
02/01
to 06/01Ariell Advanced Networks, Worcester, MA
Generate schematics using Cadence Concept. Build component libraries, place components,
manually route critical timing signals and run Specctraquest to completion. Boards are
very dense, double-sided SMT, matched routing with clock speeds in excess of 1.4 Ghz.
06/01
to presentDialight Medical Devices, Windham, ME
Generated schematics and footprints for very dense, tightly packaged, SMT PCBs. Designs
were high speed Analog with restrictive impedance issues. One plus Ghz clock speeds with
matched routing. Buried vias with active surface mounted components on both sides of the
board.
PROFESSIONAL ACHIEVEMENTS:
Have complete extensive knowledge of: PCB fabrication and assembly processes; impedance
control; Microstrip and Stripline stickups; high speed pairs; RF Restrictions;
discontinuity; coupling/parasitic capacitance; split panes; effectiveness of DFM/ DFT and
EMI counter-measures.
Complete comprehensive understanding of multi-layer high-density design, FR4/rigid, Flex,
and Radial.
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