Assistant Electrical

Ben Cordes ** Lexington Avenue

Somerville, MA ***44

******.***@*****.*** 617-***-****

Education

Northeastern University, Boston, MA

Ph.D., Electrical and Computer Engineering, ongoing

M.S., Electrical and Computer Engineering, May 2008

Carnegie Mellon University, Pittsburgh, PA

B.S. with university honors, Electrical and Computer Engineering, May 1998

Professional Experience

Research Assistant / Teaching Assistant, Northeastern University

Department of Electrical and Computer Engineering, January 2004 present

Designed, managed, and implemented a variety of research projects in the fields of reconfigurable

computing and computer architecture. Taught theory and laboratory courses to EE and CS students;

aided in development of curriculum and laboratory exercises.

Graduate Intern, Intel, Inc.

Microprocessor Architecture and Performance division, SPEARS group, January June 2009

Implemented, simulated, and analyzed potential system architecture improvements for use in future

Intel microprocessors using the PIN toolkit, C++ code, and the SPECCPU benchmark suite.

Drupal Consultant, Stonekeep Consulting, Inc.

PHP Developer and UI Consultant, Cohousing.org, June 2007 April 2008

Assisted with the transition of the Cohousing.org website from a series of custom scripts to a Drupal

content management system-based site. Wrote a custom PHP module to manage queries to an external

database. Designed user interface for cohousing directory and classified ads portions of site. Integrated

Drupal modules in PHP and JavaScript to improve the user interface.

MTS III, Sun Microsystems, Inc.

Processor and Network Products division, September 1999 February 2003

Member of the microarchitecture team of the processor design group for Millennium, a high-

performance SPARC-compatible microprocessor. Responsible for designing and maintaining blocks of

the instruction fetch unit in Verilog, making microarchitecture decisions with other team members,

assisting verification engineers with debug, and assisting circuit designers with their implementations.

Hardware Engineer I, Compaq Computer Corporation

Alpha Development Group, Corelogic Team, June 1998 September 1999

Worked with proprietary verification tools to test and debug chipset Verilog code. Gained experience

with AGP and PCI bus protocols and implementations. Processed and tested finished, synthesized netlists.

Research Assistant, Carnegie Mellon University

Department of Electrical and Computer Engineering, June 1997 May 1998

Assisted with the layout and verification of PipeRench, an innovative FPGA designed to provide an

infinite amount of virtual logic on a finite-sized die.

Graduate Research Projects

Hardware-Based Security, 2011-2012. Software-based security mechanisms at any level can always be

subverted by retreating to a deeper layer. Security measures implemented in bare-metal hardware

would be very difficult to circumvent. I am researching ways to allow execution cores to distinguish

good code from malicious and to prevent attackers from writing and executing malicious instructions,

including the use of encryption, and modifying the virtual memory subsystem.

Abstraction Layers to Enable the Management of Manycore Architectures, 2008-2011. As processor

designers produce chips containing 1,000 or more cores, the amount of work required of the operating

system to manage those resources and map threads onto them will become prohibitively large. I

explored techniques for modeling computing resources in such a way that the necessary resource

management can be divided into a high-level implementation-independent portion and a low-level

microarchitecture-specific portion.

Highly Parallel Backprojection for SAR, 2004 08. Through the support of the Air Force Research

Laboratory, we developed an implementation of the backprojection radar image reconstruction

algorithm for a reconfigurable supercomputer to meet the specifications of a military synthetic

aperature radar (SAR) system.

FPGA Application Portablity using VSIPL++, 2005 06. Every vendor of reconfigurable hardware uses a

different programming interface. This makes porting applications from one reconfigurable platform to

another very difficult. By creating an abstraction layer underneath the VSIPL++ signal-processing library

(for C++) and implementing common VSIPL++ function calls in hardware, we allow programs to be

written once using VSIPL++ and run on multiple platforms with no code changes and a simple recompile.

Embedded Neural Prosthetics, 2004. Existing neural prosthetic devices must be trained repeatedly to

match the changing brainwave patterns of a patient. This training can be accomplished using a

clustering algorithm. An FPGA implementation of the clustering can provide this function in a small

portable device, rather than requiring the user to plug into a desktop station every day. Our proof-of-

concept implementation met accuracy and speed goals.

Publications

B. Cordes, G. Schirner, D. Kaeli, Macroarchitecture: A Unifying Framework for Manycore Architecture

Research. 2010 Workshop on Microarchitectural Support for Virtualization, Data Center Computing, and

Clouds, in conjunction with MICRO'10, December 2010.

B. Cordes, Parallel Backprojection: A Case Study in High Performance Reconfigurable Computing. Master's

Thesis; EURASIP Journal on Embedded Systems, January 2009.

N. Moore, A. Conti, M. Leeser, L. S. King, Vforce: An Extensible Framework for Reconfigurable

Supercomputing. IEEE Computer Magazine, Vol. 40, Number 3, pp. 39-49, March 2007.

B. Cordes, M. Leeser, E. Miller, R. Linderman, Improving the Performance of Parallel Backprojection on a

Reconfigurable Supercomputer. 2006 MIT/Lincoln Labs Workshop on High Performance Embedded

Computing (poster); 2006 International Conference for High Performance Computing, Networking, Storage,

and Analysis (SC'06) (poster).

B. Cordes, M. Leeser, J. Tarkoff, K. Kieltyka, An FPGA API for VSIPL++. 2005 MIT/Lincoln Labs Workshop on

High Performance Embedded Computing (poster).

A. Conti, B. Cordes, M. Leeser, E. Miller, R. Linderman, Adapting Parallel Backprojection to an FPGA

Enhanced Distributed Computing Environment. 2005 MIT/Lincoln Labs Workshop on High Performance

Embedded Computing (presentation).

A. Conti, B. Cordes, M. Leeser, E. Miller, Accelerating Backprojection for SAR on an HHPC with FPGAs. 2005

Bishop's Lodge Workshop in Distributed Embedded Computing (presentation).

B. Cordes, J. Dy, M. Leeser, and J. Goebel, Enabling a RealTime Solution for Neuron Detection with

Reconfigurable Hardware. 2005 ACM/SIGDA Symposium on Field-Programmable Gate Arrays (poster);

2005 International Workshop on Rapid System Protoyping (paper).

E. Gewirtz, T. Basso, D. Leibholz, and B. Cordes, Apparatus and Method for Synchronizing Multiple Threads

in an Out-Of-Order Microprocessor. U.S. Patent #7493615

Awards

Northeastern University College of Engineering Outstanding Teaching Assistant award, 2007

Honorable Mention, 2004 National Defense Science and Engineering Graduate (NDSEG) Fellowship

Teaching Experience

EECE3230: Computer Architecture for CS Students, Northeastern U., Fall 2009, Spring 2011

Instructor of Record. Developed curriculum to follow Patterson/Hennessy computer architecture

textbook, wrote lectures, homework assignments, class projects, and exams.

ECEU323: Digital Logic Design Laboratory, Northeastern University, Fall 2005 Spring 2008

Lab Instructor. Assisted students with the implementation of a calculator on a Digilent, Inc. Pegasus

FPGA prototyping board, using the Xilinx ISE CAD tools. Delivered in-lab lectures on relevant topics,

graded written pre-lab assignments and lab reports. Rewrote and updated lab manuals in support of

hardware/software upgrades. Delivered lectures in corequisite theory course ECEU322 on latch/flip-flop

design and use, state machine design, circuit verification, and FPGA architecture.

ECEG398: Special Topics: Embedded Systems, Northeastern University, Fall 2006

Teaching Assistant. Maintained lab PC infrastructure to provide students with access to a Toradex, Inc.

Colibri embedded CPU development board. Adapted laboratory assignments to infrastructure, provided

support to students for tools and environment. Graded C++ and SystemC programming homework

assignments.

ECEU230: Computer Architecture for CS Students, Northeastern University, Fall 2006

Stand-in lecturer. Delivered series of lectures on register design, hardware number formats, and

hardware arithmetic circuts in the context of the MIPS architecture.

ECEU530: HDL for Synthesis, Northeastern University, Fall 2005

Teaching Assistant. Graded VHDL programming homework assignments, wrote in-class quizzes.

Developed material and wrote slides for a lecture on design verification using VHDL.

Society and Fraternity Memberships

IEEE Student Member, 2006-present; IEEE Computer Society, 2007-present

Eta Kappa Nu (HKN) honors society, Gamma Beta chapter

Alpha Phi Omega (APO) service fraternity, Kappa chapter

Relevant Skills

Operating Systems: Most modern operating systems including many variants of UNIX, Apple OSX, and

Microsoft Windows. Linux (Debian, Ubuntu) system administration.

Programming Experience:

High-level languages: C, C++, Java, Perl, MATLAB, Standard ML, Lisp/Scheme

Hardware modelling languages: VHDL, Verilog, SystemC

Web applications: (X)HTML, CSS, PHP, MySQL, JavaScript (JQuery)

Version control: Subversion, CVS, RCS, Clearcase

Processor Architecture Modeling:

Benchmark suites: PARSEC, SPEC2006CPU

Tools: SPIM, Pin, CMP$im, Dinero

FPGA CAD Tools:

Synplify, Xilinx ISE, Modelsim

Hobbies and Interests

Roller Derby: I referee roller derby games across the country (and internationally). It involves learning an

extraordinarily complicated sports ruleset, keeping up-to-date with the clarifications and best practices

as described by the governing bodies for our sport, and applying them on the track in high-pressure

situations. I also mentor newer referees in the New England area and am looking into becoming a

certified trainer. Along with being certified by the women's governing body (WFTDA), I'm a member of

the volunteer committee to help define the officiating program on the men's side (MRDA).

Standards-Compliant Web Design: I have a passion for using the W3C's markup and CSS validators on my

personal web design projects. My largest ongoing project is a multi-user website for tracking roller

derby referee's resumes (i.e. a list of the bouts they've worked). In the past I've done both contract and

volunteer work as a user interface, database designer, and PHP coding consultant for

DerbyNewsNetwork.com, Cohousing.org, and Stonekeep Consulting's CONGO project.

Star Island Corporation: I serve as a member of the non-profit corporation that owns and operates Star

Island, a spiritual and educational retreat center and vacation resort located on an island off the New

Hampshire seacoast. I contribute to the Alternative Energy Task Force which seeks to upgrade our

energy generation facilities while keeping a sharp eye on environment issues.

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