William Gaskell
Email: *********@********.***
Address: PO Box 110640
City: Campbell
State: CA
Zip: 95011
Country: USA
Phone: 408-***-****
Skill Level: Management
Salary Range: 60
Willing to Relocate
Primary Skills/Experience:
See Resume
Educational Background:
See Resume
Job History / Details:
WILLIAM GASKELL
PO Box 110640 Campbell, CA 95011-0640
408-***-**** *********@********.***
Multifaceted Manufacturing / Engineering Leader with more than two decades of experience encompassing all aspects of front and back-end semiconductor processing. Bottom line driven professional who consistently develops and implements processes and procedures that improve the manufacturing process and increase customer satisfaction. A globally focused manager with extensive experience in off shore and international operations. Trusted partner with divisional leaders, to ensure that manufacturing processes are cost-effective and directly support strategic business objectives. Motivational team builder, coach, and mentor.
Semiconductor Manufacturing ai Wafer Fabrication / Packaging / Testing ai ISO-9001:2008 ai Program Management ai Project Management ai Fiscal Planning / Headcount Capital Expenses ai Facilities / Office Management ai Consulting ai Start Ups ai Team Leadership / Motivation ai Inventory Management ai QC / QA ai Vendor Relations ai Cost Reduction ai Operations Management ai Process Improvement ai Scheduling ai Budgeting ai Expense Control ai Financial Analysis ai Sales Forecasting ai Customer Service ai Offshoring ai International Business
FASTRAMP / STATSChipPAC, Milpitas, CA
Engineering test development and prototype test facility, a division of Singapore based STATSChipPAC; major clients include Intel and NetLogic
Senior Planner 2002-2010
Directed and planned all preproduction and production testing of customers-owned product through wafer sort and final test for parts / engineering prototyping. Worked closely with client engineering and QA teams to determine testing parameters and schedule product testing. Worked on the development of specifications and processes to ensure consistent achievement of customer yield and quality requirements prior to shipping.
ai Developed and implemented comprehensive processes to introduce new customers to test facility and manage product introduction to test floor. Process included all aspects of wafersort and test procedures, including probe cards available and handler kits for all packages.
ai Enhanced market and customer perceptions, building brand and contributing to increased new business pipelines.
ai Established standardized documentation system to run customer product through test floor, ensuring enhanced alignment with customer goals and growing customer satisfaction.
ai Expedited prototype production through development and implementation of methodology to work effectively with customer off shore assembly facilities.
ai Contributed directly to successful ISO certification process.
WILLIAM GASKELL
PO Box 110640 Campbell, CA 95011-0640
408-***-**** *********@********.***
IMP, Inc., San Jose. CA
Leading supplier of high-integration and programmable, analog, and mixed-signal integrated circuits and wafer manufacturing services
Standard Product Line Manager 2000-2002
Responsible for Standard Product production from wafer fabrication through sales including customer relationships and product line P&L. Financial responsibility for planning and budgeting for capital equipment as required for support of sales and revenue goals. Worked closely with sales teams on cost and inventory issues, and with finance teams to develop and implement cost models. Partnered with QA for auditing / compliance with ISO 9000 requirements. Led a team of 8 direct reports including planning and customer service.
ai Coordinated with sales and customer planning groups to ensure optimal inventory levels.
o Reduced inventory turns, related costs, and write off during inventory to
o Improved customer delivery and customer satisfaction levels.
ai Offshored majority of final testing with no reduction in yields.
Test Floor Manager 1991-2000
Responsible for the wafer sort and final test operations. Introduced new test platforms and methodologies to maintain industry leading yields with strong yield to cost ratio.
ai Improved probing quality and increased yield by 10%-12% through upgrade of test floor probe equipment.
ai Partnered with industrial engineering to analyze and resolve a major issue with 64 and 84 lead PLCC test handlers. Successfully determined root cause, and significantly reduced test package issues.
ai
Previous professional experience with IMP in wafer fabrication aii (1987 -1991)
ai Wafer Fabrication Manager
Previous professional experience at Micro Power Systems aii (1981 aii 1987)
ai Process & Product Engineering Manager
ai Led successful technology transfer to Europe / Japan
PUBLICATIONS
Currently working on a Technical Study of Oxides.
PATENTS
Jointly Filed Patent on Probe Technology
EDUCATION
Chemical Engineering
Completed Certificate Program in Project & Program Management at UCSC
Job Segments: Management, Operations Management, Manager, Project Management, Business Process, Planning, Planning Management, Technology