circuit design
Resume:
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Junaid
******.***@*****.***
Mobile:
Objective
To
excel in the field of integrated circuit design and verification with
a progressive organization where career advancement and professional
growth is offered and I can prove my capabilities.
Summary
Highly
motivated professional with more than 7 years of experience, as a
Design Engineer, primarily in development of ASIC and FPGA for
Communications (LTE) and Automotive applications.
Has
good knowledge of HDL such as Verilog and VHDL. And with e-language
and SystemVerilog for verification (HVL) using eRM and OVM.
Has
also worked in embedded system with RTOS and ‘Micro C OS’.
Writing software for microcontroller application using CAN bus.
Skills
Design:
AXI/AHB/APB, 8051, LTE based designed. DSP architectures (filters)
HDLs/HVLs:
Expert knowledge in VHDL, Verilog, SystemVerilog and
e-language.
EDA
Tools: VCS Synopsis, NCSIM Cadence, Modelsim Mentor.
FPGA:
Xilinx and Altera(Quartus)
Revision
Control System: DesignSync, Subversion, CVS and Clearcase
Other
tool: Spyglass.
Programming
languages: Assembly and C/C++.
Scripting
language: Perl, bash and TCL.
Operating
System: UNIX and Windows (all)
Embedded
tools: Keil compiler, SDCC, Matlab, RTOS, uCOS
Educational
Qualifications
M.S.
(Master of Science in Microelectronics): Technical University of
Darmstadt, Germany.
B.Tech.
(Bachelor of Technology in Electronics and Communication
Engineering), with distinction: Jawaharlal Nehru Technological
University, India.
Professional
Experience(Summary)
From
June 2006 to till date Working as Design Engineer at
NewLogic(WIPRO), Austria
From
Nov 2007 to till date working as Consultant at Ericsson, Germany.
From
Nov 2004 to April 2006 Worked at Infineon, Germany.
From
April 2002 to Mar 2003 Worked as Hardware Engineer at Hyderabad,
India.
Project
Experience
Project
Name: LTE Uplink Sub-Carrier Modulator SC-FDMA
Client:
Ericsson
Role:
Design and Verification
Duration:
9 months
Responsibilities:
Concept,
design (RTL in VHDL) LTE sub-system block module (Uplink Sub-Carrier
Modulator SC-FDMA).
Verification
of SC-FDMA with SystemVerilog OVM.
Targeted
for FPGA (Altera-Quartus). Synthesis set-up.
Project
Name: Cipher Verification
Client:
Ericsson
Role:
Verification
Duration:
3 months
Responsibilities:
Worked
with AXI protocol
Extensive
verification with e-language using AXI eVC eRM.
Coverage:
functional and code coverage
Project
Name: Micronas Engine Unit
Client:
Micronas
Role:
Top level Verification
Duration:
6 months
Responsibilities:
Top
Level verification test cases for 8051
Coverage:
Code coverage
Project
Name: Ultra Low power Transmitter and Receiver
Client:
Sensor Dynamics
Role:
Block design and Top level Verification
Duration:
9 months
Responsibilities:
Concept,
design (RTL in VHDL) and verification of a configurable flash
controller for TSMC 0.18um.
Self
checking test bench(TB)
Top
Level verification test cases for 8051
Project
Name: Network on Chip
Client:
Infineon, Germany
Role:
Block design, Top level integration and Verification
Duration:
18 months
Responsibilities:
Concept,
design (RTL in systemverilog) and verification(TB in systemverilog)
of blocks( DLX pipeline processor with forwarding logic, router, AHB
AMBA-lite bus, processor)
Top
Level integration and verification
Project
Name: Embedded applications
Client:
PCDC, Hyderabad
Role:
Embedded software
Duration:
10 months
Responsibilities:
Worked
for couple of application using micro C OS and RTOS
CAN
controller and microcontroller
Personal
Profile
Languages:
English, German, Urdu (Hindi) and Telegu.
Hobbies:
Cricket, football, traveling and cooking.
Contact this candidate