Engineer Design

John J. Tobak ******@*****.***

** ****** ****, *******, ** 07940 973-***-****

Abstract A conscientious and hardworking engineer with over 8 years of experience

in Electrical Engineering including the design of digital boards for military

applications. Design experience includes component trade studies and

selection, schematic entry, PWB layout, verification testing for digital

board designs, and the generation and testing of VHDL code for CPLD

and FPGA designs. U.S. Citizen with a Secret Security Clearance.

Education

1999-2001 Stevens Institute of Technology, Hoboken, NJ

Master of Science Degree in Electrical Engineering, May 2001

1994-1998 Virginia Tech, Blacksburg, VA

Bachelor of Science Degree in Electrical Engineering, December 1998

Employment

2001-2009 BAE SYSTEMS, Wayne, NJ

Digital Hardware Development Group

• WIN-T GigE Switch Motherboard responsibilities:

Designed a program for a programmable Power Sequencer device

using the vendor-provided software applications, PAC-Designer (for

the design) and ispLEVER (for the JTAG programming of the

device). The Sequencer was designed to meet the power sequencing

specifications of the on-board Marvell 98DX243 Gigabit Ethernet

Switch device.

Designed the contents of an EEPROM used for the configuration of

the Marvell 98DX243 to support the passage of Ethernet jumbo

packets and to create a Virtual Local Area Network (VLAN). Used

an Aardvark I2C Host Adapter to load the EEPROM with register

addresses and data. When the Marvell 98DX243 is pulled out of the

reset state, it configures itself via the EEPROM.

Performed Design Verification Testing (DVT) on Motherboards

using a SmartBits test system to measure Ethernet packet loss.

• WIN-T Processor Expansion Board responsibilities:

Teamed with another engineer to design a board utilizing FPGAs,

Ethernet PHYs, and various devices for voltage regulation and clock

distribution. Also addressed I2C and RS-422 interfaces.

• MIDS-JTRS processor board responsibilities:

Generated VHSIC Hardware Description Language (VHDL) code to

configure a Complex Programmable Logic Device (CPLD) to serve as

the interface between an AMCC PPC440GX Processor and Flash

memory devices. The CPLD’s VHDL program was composed using

the VHDL editor, Emacs. The design was then simulated using

ModelSim, followed by CPLD burn-in via the vendor-provided

software application, XILINX ISE.

• F22 PIP Controller I/O board responsibilities:

Programmed the Field-Programmable Gate Array (FPGA) and CPLD

on the Controller I/O board using XILINX ISE.

Performed Design Verification Testing (DVT) on hardware prior to

delivery using an Integrated Test Adapter, cabling, and Windows-

based test system.

2000 Lockheed Martin, Moorestown, NJ

RF Group (Summer Intern)

Worked with an RF engineer to accomplish an RF board layout.

1999 Picatinny Arsenal, Dover, NJ

Automated Test Systems Division (Summer Intern)

Responsible for the organization of an electronic component inventory

within the division’s fabrication laboratory.

Design Participated in PDRs, DARs, EDARs, CDRs, and FAGAN inspections

Reviews of VHDL code.

Tools Proficient in the use of:

• Cadence Schematic Entry

• Aardvark I2C Host Adapters (I2C protocol communications)

• SmartBits (Ethernet packet loss measurement)

• PAC-Designer and ispLEVER for Power Sequencer devices

• Valor Universal Viewer (PWB layout viewer)

• XILINX ISE and Altera Quartus (for FPGA JTAG programming)

• Leonardo and ModelSim (for FPGA synthesis and simulation)

• Microsoft Office (Word, Excel, PowerPoint, Visio, and Project)

• A variety of laboratory test equipment needed for digital board-level

debugging such as logic analyzers and scopes.

Knowledgeable in:

• PSPICE, Assembly Language, C++ programming, and AutoCad.

References Available upon request.

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