Engineer Process

Resume: Pooja Thadani

Contact:

Phone: Cell 571-***-****

E-mail: ************@*******.***

Career Objective:

Seeking a full-time position in a reputed company to apply my knowledge and skills in the field of

semiconductor manufacturing and/or engineering.

Education:

Masters degree--Microelectronic Engineering Rochester Institute of Technology, Rochester, NY (2000-

2002)

Bachelors degree--Computer Science and Engineering K.K. Wagh C.O.E. GPA: 3.75 (1996-1999)

Diploma-- Computer Technology K.K. Wagh Polytechnic, C.O.E. GPA: 3.50 (1992-1995)

Industrial Technical Work Experience:

Micron Technology, Inc: (2005 –current): worked as a “Photolithography process Engineer” at the

“300mm Wafer fabrication center”. Responsibilities encompassed the following:

• Experience with semiconductor process development and integration in a 300 mm high volume

manufacturing fab, with extensive R&D experience dictated towards process improvement.

• Transferred silicon based semiconductor memory processes on 50nm, 78nm DRAM, PCRAM

and 35nm, 55nm, 72nm NAND Flash technology nodes from R&D fabrication facilities to

manufacturing facilities of Micron located in USA, Singapore, Taiwan, Italy and Japan.

• Identify, analyze and provide efficient solutions to problems/bottlenecks on photolithography

processes, which encompassed a project that doubled wafer throughput, overlay accuracy and

yield by electing ASML Twinscan Scanner coupled to a Tel Lithius track over the Canon 248nm

Scanner coupled with a Sokudo track.

• Led, devised and implemented various cost reduction projects on photo metrology platforms.

• Researched cutting edge processes like pitch doubling, double patterning to determine

fundamental limits of optical lithography.

• Implemented statistical process control charts as well as monitored and analyzed OOC/OOS

condition data to help resolve any arising process issues.

• Performed timely tool matching experiments and solved manufacturing line issues that involved

the designing of complex experiments (DOE)and ANOVA simulations to achieve the desired

results.

• Extensive data extraction and analysis using software packages such as JMP,RS/1 and Excel.

• Creation/setup of SWR’s and DPA’s for continued process related metrology development.

• Creation of reports, synopsis and trends for various product failures to compete with market

demands.

• Currently pursuing an MBA degree part-time.

Micron Technology, Inc.:( 2002 –2005): worked as a “Metrology and Real-time Defect Inspection

.”and Analysis Engineer” at the “Photo mask Technology R&D Center

Job responsibility primarily entails:

the identification, troubleshooting and resolution of yield failure mechanisms in the reticle

manufacturing process in support of current and emerging reticle technologies and include:

Defect analysis to include optical and SEM review as well as analytical techniques such as atomic

force microscopy, fissuring ion beam, and energy dispersive spectroscopy.

Extensive repairs on binary, attenuated and PSM photo mask/reticles based on yield ratio and

customer demands.

Provide summary presentations to key management and process personnel on yield limiting issues.

Creation, execution and analysis of Design of Experiments (DOE) to resolve yield issues.

Cross sectioning and SEM analysis of reticle process samples.

Recipe creation and data analysis on cd and registration metrology platforms.

Implement, monitor and analyze statistical process control charts.

Data extraction and analysis using software packages such as Excel, JMP and RS/1

Devised a few software routines that included script creation for the purpose of automating data

collection, analysis and presentation.

IBM Corporation, East Fishkill, NY (July 2001-Feb 2002): worked as a “Lithography Process

Intern Engineer” at the Advanced Semiconductor Technology Center (ASTC), Lithography.

Projects worked on, at IBM:

Qualified a Tokyo Electron (TEL), 200mm wafer track up to 30% WIP cycle generation that included

MUV resist recipe setups, KLA monitor runs, thickness inspections, CD comparisons and defect

monitor qualifications.

SPC Control on all “process of records” (POR) of exposure tools and photo-resist wafer tracks.

Determining the etch rates of a MUV resist with and without UV bake for implementation of a newer

technology for metal interconnects, a project for BEOL.

Hotplate matching and Dose to clear uniformity on a TEL 200 mm wafer track, DUV tool, comprising

of 4 precision hot plates, 4 coaters and 3 developers.

SEM and Post Develop Inspect (PDI) of developed and patterned wafers.

Designed new software in Lotus Notes for controlling the Clean room tools while offline that allowed

real time changes and tool-status updates, along with data storage abilities and in built search

engines, which saved a lot of time and improved production throughput and efficiency.

Trained at 300 mm fabrication laboratory at IBM, East Fishkill (NY), for the last one month of co-op.

Tool Operational Experience:

Nikon Steppers (exposure tools) for exposure of wafers at MUV, DUV and e-beam wavelengths.

Operation of Focused Ion Beam Scanning Electron Microscope (FIB-SEM).

ASML and TEL wafer tracks for spin coating and developing photo resists and other related

operations.

KLA Tencor tool for measuring resist thickness’, defects on wafers and related operations.

Chemical Vapor Deposition (CVD) tool for deposition of amorphous TaSiN films as a diffusion barrier.

Experience with deposition of materials like poly, nitride, LTO and various other thin films using

LPCVD and PECVD.

RCA Clean and wet etch tools, for manufacturing processes of Integrated Chips.

Ion-implant tool for doping and shallow trench isolation of CMOS manufacturing.

Analytical Operational Experience:

MEMS design for simulation software’s like “Mentor Graphics” and Co-Ventor”, for photo mask layouts

using sigma based design rules.

Extensive experience with scientific simulation softwares like “PROLITH” for photo resist

characterization and “ANOVA” for resist profile simulations and ion-implant modeling, for diffusion

mechanisms.

Used “JMPIN” and “Minitab” softwares for Design of Experiments.

Data Analysis: DI Atomic Force Microscope (AFM)

Academic Technical Experience:

Designed and fabricated an inductor and a cantilever beam using design softwares like “Mentor

Graphics” and Co-Ventor” for MEMS-design applications during the “MEMS design” course.

Built a CMOS fabrication process a project required by the course “Microelectronics-I”.

Manufactured a BJT, and optimized the gain of the transistor, by controlling design factors such as

base-width, process dependant factors etc. a part of the laboratory project for the course

“Microelectronics-II”.

Learnt and applied semiconductor parametric concepts and in-depth design considerations from the

“Semiconductor Device Physics”- I and II courses.

Applied various efficient experimental design strategies learnt, as an objective of the “Design of

Experiments” course during related work in the fabrication of labs, both in industry and in school.

Experience gained with laboratory work done in thin film deposition techniques related to vacuum

deposition of thin films, sputtering, evaporation, etching, CMP etc. as a part of the “Thin Films”

course.

Implemented a tri-layer silylation lithography process by use if an etch stop layer (SOG) for required

resist layer selectivity laboratory work for the course “Lithography-I” and “Lithography-II”.

Learnt use and operations of most of the microelectronic manufacturing tools, by performing many

jobs on a variety of them objective of the courses namely “Microelectronics Manufacturing-I and

Microelectronics Manufacturing-II”.

Presentations:

“Fabrication of a Condenser Microphone by Multi User Integrated Chip Service”.

“A Bruce Furnace analysis of Defect Density Growth Rate for growth of wet, dry and gate oxides”.

Worked at Crompton Greaves Ltd, India in the “SAP” department and also designed automated

software namely “Automated Current Transformer Designs” (1995-1996).

Computer Skills:

Extensive experience with all MS windows operating systems, MS Office.

Programming in Lotus Notes 123, Visual Basic, Foxpro, Oracle, and MS-DOS based terminals.

Taught C, C++, Visual C++ and Oracle (RDBMS) at Aptech Computer Institute.

References: Available upon request.

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