Design Engineer Project

Summary:

* + years of experience in Hardware design, Development and Verification.

Responsible for building FPGA designs from Scratch. Work mainly involved RTL coding

& Verification.

E

Experience:

Hardware Design Engineer

Valco Cincinnati Aug08-Dec08

Ohio, USA.

Responsible for the design of color code project using Altera s Cyclone II FPGA

( QuartusII).Implemented the design at 40 MHz with 90% utilization. Developed RTL

codes (Verilog), Created State machine for reading the red, blue & green values

.Designed a digital circuit for the edge detection. Developed schematic to include

test mode. Developed RTL codes to design threshold registers, position registers,

read/write only registers, counters, Measurement registers, Shift registers,

multiplexers. Generated interrupts when there is a color change .Performed

functional simulation using the integrated vector waveform editor for the various

schematics and verilog codes. Performed timing verification for all the schematic

&HDL codes using Classic Timing Analyzer in Quartus II. Performed Real time

debugging using signal tap logic analyzer to remove errors. Displayed the values

of registers on the hyperterminal using serial communication. Performed board level

testing. Used Oscilloscope to check the bitstream . Performed soldering at board

level. Created & updated Documentation for the project.

Designed, implemented and verified a pulse width modulator for the valve driver.

The purpose of this project was to eliminate mixed copy. Developed ABEL and verilog

codes for the state machine and verified it through integrated ABEL Editor and

using the stand alone Modelsim for the verilog model. Performed timing analysis,

synthesis through integrated synplify, assigned pin configuration and downloaded

to the lattice MACHXO device.

Logic Design Engineer

Orbit Solutions June 06- July 07

H

Hyderabad, India.

Designed & implemented an 8point FFT (fast Fourier transform)at 100 MHz on

Xilinx-VirtexII Pro Device. Developed VHDL Codes for the eight 14 bit shift

registers and passed it to the 8 point butterfly network to get the spectrum of the

input signal. The magnitude values were stored in the Power PC 405 registers and

read out through C Program and displayed on the Hyper terminal using serial

communication.

Responsible for including UART and Counter module for an application on Xilinx-

VirtexII device .Designed implemented the transmitter, Receiver using verilog and

functionally verified. Clock divider and Baud rate selector were also included to

select a baud rate from a range and to supply an internal clock for the baud rate.

Developed verilog code for counter module to synchronize the scanner and the

trigger signal.

Designed a sequential block for a part of a smart card security system. A state

machine code was written in VHDL and would deliver the output if the entered

sequence matches the password of the machine and in the case of false password it

would deliver an alarm sound. The designed was implemented and verified on the

Altera Flex chip.

Programming (INTERN)

ISP technologies April 05- Dec 05

Bangalore, India.

Worked on developing RTL codes like multiplexers, decoders, priority encoders, ALU

& small state machines for ASIC.

Developed RTL code for hamming encoder and decoder. Generated test patterns and

determined fault coverage using synopsis DC compiler and ATPG pattern generator.

Developed test benches for various designs in VHDL for design verification

Worked on windows programming using C++ for creating dialog box using MFC built in

functions.

U

Updated Electronic Documentation for various projects.

Professional lab work:

Drawing Schematic, layout & performing transistor level simulation using Cadence

Composer Schematic & Cadence Virtuoso for the TSMC 0.24 um technology.

Performing Logic Synthesis and optimizing power, area, delay using Cadence

Encounter RTL Compiler.

Good understanding of communication modulation techniques like amplitude

modulation, Frequency

Modulation & PCM (Pulse coded Modulation).

Working Knowledge of Embedded Microcontrollers from freescale.

Knowledge about DDR2 memory.

PCB schmetic capture and layout using Orcad.

Experience with debugging & testing instruments like Logic Analyzers, Spectrum

Analyzers, Oscilloscopes.

Worked with High speed designs and has knowledge about serdes .

Skills:

EDK Xilinx-VirtexII, VirtexII pro, Alter a - Cyclone II,

Lattice-MACHXO.

HDL Verilog, VHDL, ABEL, AHDL.

Simulation Modelsim, SynopsisVCS, Cadence NC-VHDL,Matlab.

Synthesis RTL compiler, DC compiler, Synplicity .

Place& Route Xilinx Implementation tools, Altera-QuartusII.

Software C,C++,Embedded C++.

Education:

Master of Science, Electrical Engineering

sep07-Aug08

Wright State University,

Dayton, OH.

G

GPA: 4.0

Bachelor of Engineering (B.E) in Electronics and Communication Aug02-may06

Osmania University, Hyderabad, India

GPA: 3.65

References:

Available on request.

U

U.S Permanent Resident.

A

Contact this candidate