Engineer Design

PUSHPA PRABHUSWAMY

****, ******* *****, *********, ** 94086

******.**@*****.*** Phone(C): 224-***-****

HARDWARE ENGINEER

Strong background in digital design and verification.

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2+ years of professional experience in ASIC/SOC/FPGA design and verification.

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Experience in RTL coding using Verilog and VHDL.

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Experience in ASIC Verification using Open Vera, System Verilog.

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Familiarity with industry standard methodologies – RVM, OVM, VMM.

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Knowledge of ASIC Flows, Physical Design, Timing Analysis, EDA tools and hardware debugging.

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Master of Science (Computer Engineering) and Bachelor of Engineering (Electronics and communication).

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Proficient in programming and scripting – assembly, C, C++ (Object Oriented), Perl.

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Individual contributor, Team player, enthusiastic learner.

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SKILLS

HDL/HVL: VHDL, Verilog, SystemC, Open Vera, System Verilog.

Methodologies: RVM, OVM, VMM.

Programming Languages: C, C++, 8/16 bit Assembly Language, MATLAB.

Scripting Languages: PERL, Python, Linux shell scripting.

EDA Tools:

ASIC: Design Compiler, Certitude, Spyglass, Design Analyzer.

FPGA: Xilinx -ISE-Virtex II FPGA Design Flow, System Generator, Altera- Quartus Cyclone II.

Simulation: VCS, Debussy, Questasim, NC-Verilog, Discovery Visualization Environment, ModelSim,

Simvision, Pspice.

Physical/Layout: Analog Artist, Virtuoso, Hspice, PrimeTime, Assura (LVS/DRC).

Others: ARM RVDS, Simulink, Code Composer Studio, Microvision, CVS, Visual Studio, CSCOPE.

PROFESSIONAL EXPERIENCE

Indus-USA, Inc

Embedded Engineer (Apr 2009-Present)

Summary: Individual contributor in the development of a prototype for hand-held CAN Bus Analyzer based on

Windows CE platform for ARM-9 core.

Responsibilities:

a. Design and development of GPIO, SPI device drivers to interact with the CAN controller.

b. Development of application and GUI using VC++(MFC).

c. Multithreaded programming for Windows CE.

CISCO Systems, Inc

Hardware Engineer(Design Verification Engineer), ASIC Team (Jan 2008 – Apr 2009)

Summary:

• I/O aggregation ASIC for Router: Involved in pre-silicon block level verification using Open Vera and

Reference Verification Methodology(RVM) to construct a constrained-random, transaction-level, self-

checking, coverage-driven test environment.

• Awarded Individual Excellence Award.

Responsibilities:

a. Improving test environment through additional test cases and scenario generation to achieve complete

coverage.

b. Perl scripting for automated testing.

c. Ownership of block level regressions, triage of bugs and use of bug tracking tool.

d. Defining Functional Coverage items and running constrained and random tests to get maximum coverage.

e. Code Coverage analysis and merging results for dependent blocks.

f. Evaluation and analysis of the testbench through Certess Certitude.

g. Investigation of System Verilog Assertion (SVA) requirements and methodology.

h. Use of Test and Coverage plans to verify all features.

i. Detailed study of interfaces such as PCIe(PCI Express), SPI, GigE(Gigabit Ethernet), I2C.

CISCO Systems, Inc

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Pushpa Prabhuswamy ***-**-****

******.**@*****.***

Intern, ASIC & HW Design Tools Team, Access Router Technology Group (May 2007 –Aug 2007)

Summary: Development of PERL/Shell scripts to develop in-house tools to monitor team’s computing

resources.

Responsibilities:

a. Developed scripts to monitor large network storage partitions and servers.

b. Developed application shell scripts and Perl programs that posted and plotted statistics (GNU plot) on the

web with overload notification sent to administrative personnel.

c. Developed Perl scripts to automate regressions through GUI.

Electronics and Radar Development Establishment (LRDE)

Project Assistant (Jan 2006–Jun 2006)

Summary:

• Design of various FPGA based subsystems of RADAR

• Modules included in the Xilinx block set library for RADARs.

Responsibilities:

a. Logic Design and Synthesis using VHDL and Xilinx Virtex II Design flow.

b. Use of MATLAB and Xilinx System Generator Tool for implementation of mathematical functions.

c. Detailed study of RADAR functionality and internal communication.

EDUCATION

Master of Science in Computer Engineering, Dec 2007

North Carolina State University, Raleigh, North Carolina.

Bachelor of Engineering in Electronics and Communication Engineering, July 2006.

R.N.S. Institute of Technology (Visvesvaraya Technological University), Bangalore, India

PROJECTS

ASIC Verification: System Verilog based verification of LC3 (RISC) architecture inclusive of Cache functionality

– Functional Verification and Coverage using concepts of constrained random testing, object oriented

programming, layered test benches and inter-process communication. Use of checkers/scoreboard to verify the

functionality.

ASIC Design:

a. Sudoku Solver – Implementation and Synthesis of Verilog based Sudoku Solver. Logic design, High level

implementation and exploration of various algorithms using C.

b. Sub Band Encoder for speech signals – Speech analysis, decomposition and reconstruction of a speech

sample using polyphase filters, delta modulation and investigation of various architectures/algorithms and

implementation(fixed point, floating point) in Matlab, System C, Verilog and System On Chip Tools.

Computer Design and Technology:

a. Construction and analysis of a simulator for an out-of-order superscalar processor based on Tomasulo’s

algorithm.

b. Cache Simulator – Design and Simulation of Caches with Victim Cache suited for SPECint95 benchmarks.

c. Designed and developed a comparative analysis of bimodal, gshare and hybrid branch predictor structures

suited to SPECint95 benchmarks through simulation using C.

VLSI Design and Technology: Designed and created a full custom layout of a Multiply-Accumulator Chip as an

alternative to place and route method, with optimized area and speed. Involved in complete logic design, circuit

simulation, floor planning, parasitic extraction and testing for 0.18u Technology along with DRC and LVS

nd

checks. Was judged the 2 best design out of 30 designs of the class.

Communication:

a. Design of a cellular system for a new TDMA based standard designed according to the given specifications.

b. Simulated the behavior of end to end packets delivery in a virtual network – Implementation in C

TRAINING & WORKSHOPS

Training in usage and implementation of Vera OOP verification environment using Reference Verification

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Methodology with VCS Verilog RTL simulation tool.

W orkshop to solve design issues through Atrenta Spyglass.

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TECHNICAL ADDENDUM

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Pushpa Prabhuswamy ***-**-****

******.**@*****.***

VHDL, Verilog, SystemC, Open Vera, System Verilog

HDL/HVL

Verification Methodologies RVM,OVM,VMM

Programming Languages C, C++, 8/16 bit Assembly Language, MATLAB, VC++ (MFC), C#.

Scripting Languages PERL, Python, Linux shell scripting.

Operating Systems Sun Solaris, Linux, Windows 98/NT/XP/2000, Windows CE.

Microcontrollers/processors Intel (8085/8086/8051), Motorola M16C, Atmel AVR, PIC, TI DSP, ARM-9.

Protocols PCIe(PCI Express), USB, GigE(Gigabit Ethernet),SPI,CAN,LIN,I2C

Tools

Design Compiler (Synopsys), Certitude (Certess), Spyglass (Atrenta), Design

ASIC

Analyzer (Synopsys).

ISE-Virtex II FPGA Design Flow (Xilinx), System Generator (Xilinx), Quartus

FPGA

(Altera).

VCS (Synopsys), Debussy (Novas), Questasim (Mentor Graphics), NC-Verilog,

Simulation

Discovery Visualization Environment (Synopsys), Model Sim, Simvision

(Cadence), Pspice (Cadence).

Analog Artist (Cadence), Virtuoso (Cadence), Hspice (Cadence), PrimeTime

Physical/Layout

(Synopsys), Assura-LVS/DRC (Cadence).

Oscilloscope, Logic Analyzer, Signal generators, Signal analyzers, Spectrum

Debugging Tools

analyzers.

Real View Developer Suite (RVDS) for SOC (ARM), Simulink (Matlab), Code

Others

Composer Studio (Texas Instruments), Opnet, Visual Studio, Keil Microvision,

CVS, CSCOPE.

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