Engineer Process

JAmes J. Heaps-Nelson

**** **** ******** ******* ******* #1096

Phoenix, AZ

Phone: 832-***-**** e-mail:

************@*****.***

WorK Experience:

SEMICONDUCTOR PATENT EXAMINER, USPTO JAN 2009- JUNE 2009

ALEXANDRIA, VA

Examined patent applications across a wide range of semiconductor

applications including power semiconductor, LED and semiconductor laser

applications

Senior Process Engineer, Intel Mar 2006-Dec 2008

Chandler, AZ

Qualified HDPCVD systems for on schedule 300 mm startup on STI and ILD0

processes

Resolved difficult issues resulting in substantial yield improvements

on STI and ILD0 200 mm processes. Responsible for 30% particle reduction

and yield impact amounting to $5 million cost savings at the module level

Process Integration Engineer, IBM- Feb 2004-Jan 2006

East Fishkill, NY

Received a patent as a co-inventor on a contact forming process

Integration owner for contact module developing 65nm SOI process

Coordinated resolution of line-stopping contact etch issues

Helped facilitate dual stress liner development in 65 nm node SOI

Process Engineer, Intel- Feb 2001-Jan 2004

Hillsboro, OR/Albuquerque, NM

Responsible for the transition of the 300 mm HDPCVD PSG ILD0 layer from

development to manufacturing

1260 Seed Engineer for HDPPSG ILD0 and nonseed 1262 engineer for HDPPSG

ILD0

Supervised UltimaX Chamber upgrades on PSG01 and coordinated the

resolution of several difficult requalification obstacles

Source inspected six HDPCVD machines at a vendor site and drove hundreds

of defect issues to resolution

Qualified two HDPCVD systems in the first high volume 300mm wafer

fabrication facility in the world

Layer owner over a challenging dielectric deposition module during a

300mm semiconductor startup

100% quality record during two years of layer ownership with no wafer

losses

Manufacturing Engineer, Applied Materials- Dec 1999- Feb2001

Santa Clara, CA

Effectively teamed with marketing, project management and manufacturing

groups to deliver Producer CVD machines to customers and met 100% of

manufacturing commit dates

Responsible for solving major gas panel outsourcing issues

Collaborated with R&D groups on prototype machines

Provided general Oracle technical assistance to AMAT engineering groups

Resolved major manufacturing roadblocks on the 300 mm Producer Platform

for a major Taiwanese account

Configuration Engineer, Applied Materials - Oct 1997- Dec 1999

Santa Clara, CA

Employee of the Month (April, 1999) in the Planarization and Dielectric

Deposition group

Responsible for HDP, P5000, TEOS/Silane and SACVD bill of materials

configuration

Transitioned HDP platform from pilot to volume manufacturing

Education:

M.S. Chemical Engineering and Petroleum Refining, Colorado School of

Mines- 1993-1996 Golden, CO

Thesis: Characterization of Lewis and Bronsted acidity of vanadyl

pyrophosphate (VPO) catalysts

Operated and maintained a bench-scale catalytic oxidation reactor and

analyzed reaction products using an HP 5890 Gas Chromatograph

Created and operated an experimental apparatus to study the adsorption of

basic probe molecules on VPO catalysts in conjunction with FTIR analysis

using a Bio-Rad FTS-40 IR spectrometer

B.S. General Engineering, Harvey Mudd College- 1989-1993

Claremont, CA

Co-author of a 200 page advisory report to NASA/Ames Research Center

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