Design Engineer
Resume:
Horace Joseph Sklar
*******@*****.***
415-***-**** (c) 415-***-**** (h)
San Francisco, CA 94121 United States
www.hjsklar.emurse.com
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OBJECTIVE:
To achieve client loyalty on groundbreaking technology projects through
excellent project management and product design.
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SUMMARY:
In 1986, Mr. Sklar started his ASIC design services company after
spending twelve years working in military defense organizations. Mr.
Sklar has extensive program, client and resource management, marketing,
proposal, and customer experience running his own company for over 23
years. He has strong organizational and interpersonal skills.
His technical expertise spans systems architecture, hardware design,
test and integration experience in: spacecraft electronics, military
communications, digital signal/image and neural net processing,
electronic/anti-submarine warfare, control, and includes other areas
such as built-in-test and artificial intelligence. Mr. Sklar has design
experience with over fifteen ASIC gate arrays using VHDL, DxDesigner.
Orcad, synthesizer, static/dynamic timing and floor plan CAE tools. His
hardware and firmware experience spans bit-slice, microcontrollers, and
numerous multi vendor COTS, DSP chips, and application specific analog
and digital designs.
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EDUCATION:
BSEE Magna Cum Laude, Electronic Engineering, Princeton University
(9/1969 - 5/1972)
EE (thesis open), Communications, Massachussetts Inst of Technology
(9/1972 - 5/1975)
Six courses while in High School, Mathematics, University of Miami
(9/66 - 5/69)
4.0 Grade Point Average-
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TRAINING:
CMDE ASIC Design Workshop, LSI Logic 1992
DxDesigner/VHDL Workshop, Viewlogic 1991
Program Management Workshop, TRW 1986
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KEYWORDS:
ASIC FPGA Xilinx Actel VHDL DSP DxDesigner Matlab Simulink Algorithm
Architecture Trades CompactPCI VME Image Processing COTS PMC SBIR
Project Management Systems Proposals
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SKILLS:
CAE Tools DxDesigner/Viewlogic, LSI Logic MDE, OrCAD Capture, PADS PCB,
MATLAB, ModelSimSE, Xilinx ISE, Timing Designer.
ASIC / FPGA / DSP / BUS Xilinx Spartan, 40xx, Actel, TI DSPs, AT&T 32c,
CompactPCI, PMC, TIM, VME/64, LSI Logic
Language/OS VHDL, PERL, Tcl/Tk, Firmware, Assembly, C, Unix Solaris,
Windows
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WORK EXPERIENCE:
Silicon Technology Labs, Owner, San Diego, CA (10/1986 - 6/2009)
Power line distribution simulations using Matlab Simulink and SimPower
System supporting hydro-electric 8 MW power plant in northern Peru
grid.
Near Field Infrared Experiment Systems satellite payload Lead Hardware
design of VME64 Spacecraft Interface using ACT2 RadHard FPGA with
VME/MBLT transfers, and VME64 Image Processor of target payload
Electronics Control Module. DxDesigner CAE Toolset with Actel Silicon
Explorer II.
Technical project lead for GSTAMIDS Data Acquisition Subsystem (DAS)
explosive detection system. Perform subsystem requirements analysis,
architecture development and design, COTS selection/integration, and
hardware design of a 6U CompactPCI Data Acquisition Module. Design
features 32-bit, 33MHz PCI Bus-Master Interface with 9-channels DMA,
Intel 21154 PCI-PCI Bridge, 8-channels 12-bit, 10MHz Rx Data
Acquisition with dithering, Dual 20 MHz Tx channels, dual Intersil
5216, and support of Xilinx Spartan-II FPGAs during I&T. DxDesigner
EPD 2.0 tool suite, Xilinx ISE 4.2 and PCI and FIFO IP cores.
Develop Air Force Research Labs Portable MSTI-3 Payload Simulator.
Architect and design portable subsystem and board using two Actel
ACT-3 FPGA that accept three high speed video telemetry, command,
sensors, housekeeping, and control with a PCMCIA interface to laptop
and three real-time B&W video outputs. DxDesigner and Actel Explorer
tools.
BMDO Miniature Sensor Technology Insertion-3 system architect/
designer for VME32 space-based payload Electronics Control Module
consisting of design, simulation, test and integration of three
fault-tolerant TMS320C30 camera and Spacecraft Interface PWA utilizing
Actel ACT-2/3 FPGA and TI DSP processors. DxDesigner and ACT tools.
Vacuum, temperature, acceptance testing at Edwards AFB.
System Administrator and VHDL benchmark support for three LSI Logic
300K technology ASICs, perform verification VHDL test benches and
backend release process simulation, ATP, floor planning and production
test vector for ATF program.
Design Xilinx 4010 CUE FPGA for Air Force Mil Parameter Encoder
application, 25 MHz controller with 12K gate density using DxDesigner
and Xilinx ICE tools. Performance of 25 MHz required custom floor
planning and placement of individual critical path cells at Xilinx
Main office site in Milpitas.
Develop 20 MHz I/O Sbus Board using two Xilinx 4013 FPGAs using
DxDesigner/Xilinx FPGA tools. I/O Board provides for crosspoint
switching of 6 full-duplex serial, parallel, and HotRod serial busses,
with dynamic retargeting and data reformatting for a full 40M
samples/sec.
Manage design of Gould/AMI Scan converter ASIC, 30K density, for
graphics display system. Design used Viewlogic frontend simulation and
AMI backend tools and Model VHDL Simulator for golden simulation.
Systems and hardware design and prototype of general purpose 1Kx1K
color image workstation hosted on Windows/PC and Unix/Sun. Design
includes Crunch-860/VME co-processor product and SBIR CMP Vision Image
co-processor ViP daughter board utilizing two LSI Logic ASICs. Gate
arrays consisted of 80K (ViPIO) and 110K(ViP) gate density, designed
using DxDesigner (VHDL & ViewSim) for front end simulation at the ASIC
and board level, and MDE for timing and placement. ViPIO ASIC design
performed Dual-Bank DRAM address generation and i860 control
interface, while ViP consisted of a patented 8x8 systolic array of
processing elements operating with a 30 Mhz clock to implement
real-time image algebra operations.
DARPA SBIR Army Battlefield Neurocomputer systems design and SIMD
Neural Array Processor (SNAP) board and ASIC design of 100K gate ASIC
utilizing LSI Logic MDE toolset. Architecture consists of
loosely-coupled, SIMD floating-point array using AMD 29000
Microcontroller.
Design and prototype DATA I/O DT-Connect compatible image interface
daughter board. Design supports three-level pipeline, zero wait state,
full-duplex, high speed FIFO interfaces, at 80MBytes/sec bursts rate
to the Crunch-860/PC & VME product. Design 48 MB, 0-wait state, three
level pipeline DRAM daughter board for both Intel-860 Crunch-860/PC &
VME products. Design supported 160MB/sec sustained throughput on-page.
DxDesigner tools.
Codesigner for reverse engineering of HP LaserJet IIP and III
compatible memory board and prototype.
Report functional and temperature test of NEC ASIC devices as per
customer specifications.
Develop JTAG compatible design and concepts for gate array
implementations using DxDesigner.
Re-design and integration of custom Integraph VME-VME DMA interface to
support 7 MBPS transfers.
Propoasl lead systems engineer for a 32-channel Fast Time Analyzer
System (FTAS) (ASW) proposal win based on innovative architecture.
Efforts included signal processing algorithm development such as FFT
and Polyphase Filters with Matlab and Hardware-in-the-Loop support,
architecture trades with various DSPs (320C30, 56000, and 29000) and
application specific devices, coding, and system development concepts.
Proposed architecture reduced the new design LRUs from 12 down to a
single board, 8-stage, loosely-coupled array of identical DSPs
partitioned along data rate requirements via high speed serial IO.
System design and performance using Matlab allowed for incremental and
independent debugging of system, software, and hardware from remote
sites. Design firmware code and test on FTAS real-time AT&T 32C DSP
serial systolic architecture for ASW acoustic DSP narrowband
algorithms. VME testbed with PC-based tools: Debugger, Simulator,
Assembler. Used MATLAB and RTW for algorithm.
Develop, produce 22 FTAS SCSI-2 Disk Array Units utilizing quad 1.6GB
disk arrays in a 19" rack.
DirectTV desktop Xilinx FPGA VHDL design, code, benchmark and hardware
test.
Reverse design of Ethernet Switch using Actel FPGA design environment
and DxDesigner.
Lead system engineering and evaluation of alternate MIMD
massively-parallel neural-net architectures and trade-offs leading to
SBIR proposals. Architecture study addresses the range from fully
hard-wired physical neural nets to virtual machines using numerous
neural net paradigms. Technology assessments included custom ASIC,
FPGA, and DSP based architectures.
System technologist responsible for developing published reports
published in Semiconductor Technology & Assessment Program. Reports
cover systems technology: workstations, super/mini and supercomputers.
Device technologies addressed: BiCMOS, Memory, ASICs, and 32-bit
Micros. Conduct industry surveys addressing markets, performance
drivers, architectures, and technology trends.
Peace Shield Systems Lead analyst for modular, secure-voice/data
equipment. Architecture consisted of loosely-coupled, multi-site,
multi-processors (TMS320C25 DSP and Harris I/O processor (6303)).
Modularity allows for small number of unique processor and peripheral
modules configured into eight separate systems spanning secure-voice
terminals, data and FAX terminals with small number of Line
Replaceable Modules. Design comprehensive built-in-test (BITE) system
concept.
SCOTT Communication satellite system senior software engineer for DSP
algorithms design, high-level descriptions (HDL), ADA PDL
documentation, C programming (HOL), and assembly code for TMS320C25
DSP. Perform code verification on TI TMS simulator tools in a VAX/VMS
environment.
ALQ-131/VHSIC Tranmit Control Assembly Lessons Learned report
resulting from improved availability of the ALQ-131 Transmit Control
Assembly and the first-time integration of ASICs, VHSIC and BITE.
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TRW / MEAD, Senior Staff Engineer (SPM), San Diego, CA (3/1983 -
10/1986)
Air Force ALQ-131 VHSIC Transmit Control Assembly Subproject Manager,
leading team of fifteen Work Package Managers and ASIC/FPGA hardware
engineers for hardware/software design and CAE environment
incorporating ten ASICs and VHSIC technologies into an electronic
warfare pod.
IR&D Principal Investigator for Maintenance and Diagnostic System
(MADS) to support generic VHSIC, ASIC, and off-the-shelf digital &
analog technology BIST/BITE. Conceptual development and design of BIST
ASIC to execute pseudo-random generation and signature-analysis
techniques.
IR&D Rules Expert on Advanced Avionics Availability Improvements
program to develop real-time rule-based Expert diagnostic system to
perform fault diagnosis and isolation to Line Replaceable Unit.
Redesign AMD 2900 based bit-slice array processor for QAM/QPSK/FSK
multimode modem.
Signal Processor team leader for Advanced Tactical Fighter proposals.
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ITT / Defense Communications Division, SMTS, San Diego, CA (1/1981 -
3/1983)
System analysis and architecture trades, algorithm development and
simulation, hardware and software design code for Tactical fighter
speech recognition front-end employing the TMS32010 DSP and 68000.
C-algorithm development on VAX/780 UNIX host for recursive and
non-recursive filter-bank and Linear Predictive Coding techniques.
Voice Recognition algorithm designs and provided Texas Instruments
support on hardware design of TMS32010 DSP. Design of C-based TMS32010
Simulator.
Design of Secure Voice terminal consisting of LPC Vocoder and 16-KBPS
wire-line modem. 16KBPS QPSK Wire-line Modem system architecture and
hardware design. Design incorporated custom AMD 29000 bit-slice
architecture for real-time signal, processing and Motorola 68K host
embedded processor. Tightly coupled design with 29000 bit-slice
executing high level macros.
System design engineer on advanced 1990s secure voice YOHO terminal.
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Rockwell INTL / Collins Radio, Engineering Scientist Level IV, Anaheim,
CA (8/1978 - 1/1981)
Gained important project management skills and interpersonal skills
motivating a team of ten engineers as a hardware project manager for
new HF & UHF modem communications product lines. Develop requirements,
design, build and code bit-slice array and control I/O processors
satisfying throughput of real-time DSP techniques for LINK-11 (NAVY),
TADIL-A, TAOC-85 modes.
Design analog/digital peripherals that will allow, in conjunction with
processors, multitone (QPSK/Kineplex) and adaptive single tone HF in a
multimode and simultaneous mode of operation. Modem features BITE
subsystem.
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GTE Sylvania, Research & Development Engineer, Needham, NA (6/1975 -
8/1978)
First commercial design of 5-MHz, 40-bit wide horizontal instruction
code 2900 bit-slice processor and microcode for multi-mode PSK
satellite modem utilizing high-speed analog front end half-baud
integration algorithm.
Hardware lead engineer for Navy secure CVSD communications subsystem.
Design and macro/assembly, and C program of BITE subsystem based on
Z80.
Algorithm benchmark and code DSP algorithms for Seafarer program on
AN/UYK-20. Design control software for 8080 and COSMAC microprocessors.
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Draper Labs, Research Assistant, Cambridge, MA (9/1974 - 5/1975)
M.I.T. research assistant on binocular robot vision project to develop
stepper motor hardware control and PDP-9 minicomputer hardware
interface, algorithm and software development.
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PUBLICATIONS:
"Embedded expert systems for fault detection and isolation (in avionics
systems)"
Smith, Carolyn and Sklar, Horace
Digital Avionics Systems Conference, 7th, Fort Worth, TX; United States;
13-16 Oct. 1986. pp. 613-617. 1986
BiCMOS Technologies Trends
STAP Program, TTG, 1987
32-bit Processors Trends
STAP Program, TTG, 1987
Advanced Avionics Availability Improvements
TRW IR&D report, 86/85, Project No. 86121026 & 8512026
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AWARDS AND HONORS:
Patent # US5471627, "Systolic array image processing system and method"
Dr. R. W. Means and Horace J. Sklar, filed 5/26/1992
IEEE Gordon Bell Award for Price/Performance
HNC SNAP System/Hardware Design win, 1993
ARRIVA Award
TRW/MEAD, SPM Performance excellence for ALQ-131 VHSIC Transmit Control
Assembly program
Centralized Slew Rate Control for NTDS I/O
Rockwell Trade Secret
Silver Knight Nominee for Mathematics
National Honor Society, La Salle High
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CLUBS AND ORGANIZATIONS:
IEEE Member
US Table Tennis Organization
Texas Instruments Registered DSP Consultant
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INTERESTS:
US Citizen, Born in Cuba, Inactive SECRET Clearance. Fluent in English,
Spanish, conversant in French. Classically-trained pianist, USTTA table
tennis & billiard player, XBOX 360.
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REFERENCES:
http://www.hjsklar.emurse.com/hjsklarref
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