Design Engineer

Younes CHOUIA

** *** *** ******** ******** Hill ON - Tel: 647-***-**** -

******.******@*******.**

I am a Senior Layout Engineer with a Master Degree and expertise of 6 years,

proven on various ASIC designs among which the world's best audio Digital to

Analog Converter. I have a wide range experience in Analog and Mixed signal

Layout design including DRC, LVS, DFM and Antenna Checks, through many

Technologies & Processes to complete projects on time and within budget. I also

provided RC extractions and application support for physical design.

OBJECTIVE

To obtain a challenging position in the field of ASIC / VLSI Engineering, using

my in depth knowledge and experience in custom circuit layout, ASIC Design of

high speed CMOS designs.

KEY QUALIFICATIONS

Mixed Signal and Analog Design On-Time and Scheduled Goals

Mentoring and Teamwork Analytical and Effective Solutions

Virtuoso Layout/Schematic Editor Flexibility and Communication Skills

Avanti Hercules/ Mentor Caliber DRC/ LVS Physical Design Planner/Silicon Ensemble

Avanti Star-RC ModelSim, Matlab

Mentor Analog Artist/Cadence Layout-XL Languages: C, VHDL, Verilog-A

Employment History

Analog Designer 2 2009 - 2010

[AMD Inc., Toronto ON]

Performed Layout design of many different Standard cells including DRC/LVS/DFM

and Abutment checks for many Technologies TSMC32, TSMC28 and GF28.

Contributed in different projects by Performing Layout design of many Analog IPs

like Comparators, Pads, and Power blocks including DRC/LVS for Technologies like

TSMC32 and GF28.

Changed Layout of some IPs from TSMC32 to TSMC28 for some test chips.

Implemented some new IP architecture to be used in many chips.

Senior Layout Engineer 2005 - 2008

[ESS Technology, Kelowna BC]

Performed Layout design including DRC/LVS, Antenna Checks also RC extractions and

post-layout simulations of different sub-blocks of RF Micro-Tuner Project

implemented with CMOS 0.15um GSMC process.

Completed Layout design of 11Bits 110MHz pipelined ADC with CMOS 90nm TSMC

process including DRC/LVS/DFM and Antenna Checks.

Contributed in the Blu-Ray red laser Project by Layout design and Verifications

of Digital Frequency Generator with CMOS 90nm TSMC process.

Performed Layout design, Verifications and RC extractions of 1.2V Band-gap

Voltage Reference with CMOS 0.15um TSMC process used in Buck-Boost Regulator

Project.

Implemented Critical changes based on post-layout simulations of RC extractions

of ESS World best Audio DAC with CMOS 0.15um TSMC process.

Contributed in IBM 0.13um 2M Pixel Camera chip Project by Layout design and

Verifications of Reference Voltages and Currents for different circuits.

Implemented Comparator and LDO circuits with CMOS 0.15um GSMC process used in

SLIC Project.

Performed the Layout design and Verifications DRC/LVS/DFM, Antenna Checks and RC

extractions of Various Analog IPs.

Member of Research & Development Team 2003 - 2005

[Prompt Quebec, Montreal QC]

Contributed in the Design of 14 bits, 50MS/s CMOS Front-End Sample and Hold

Module Dedicated to a Pipelined ADC with CMOS 0.25um TSMC process.

Performed the Layout design (DRC/LVS and Antenna Checks) & RC extraction of

10Bits pipelined ADC at 50MHz with CMOS 0.25um TSMC process.

Contributed in the Study and analyses of high-speed analog to digital converters

(ADCs) dedicated for large band wireless communication receivers.

Member of Research Team 2002 - 2004

[GRM, Montreal QC]

Performed the Optimization of Analog circuits Using Verilog-A for high

performance purposes.

Contributed in the Layout design of two microchips pipelined and interleaved

ADC's with 0.25um process.

Member of POLYSTIM research group in biomedical applications.

EDUCATION

Master of Science, Electrical & Electronics Engineering, 2004

Montreal University ( cole Polytechnique), Montreal QC

SCIENTIFIC PAPERS

"14 b, 50MS/s CMOS Front-End Sample and Hold Module Dedicated to a Pipelined

ADC", the 47th IEEE International Midwest Symposium on Circuits and Systems,

25-28 July 2004. pp. I-353 - I-356.

"Low Power, Low Voltage, 10bit-50MSPS Pipeline ADC", scientific journal to be

submitted after testing the manufactured chip.

"A new technique for designing high performance front-end Sample and Hold

circuits", submitted for the 16th International Conference on Microelectronics

(ICM), 6-8 December 2004.

INTERESTS

Soccer Traveling

Reading Music

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