Engineer Design
Resume:
DIMITRIS K. FOTAKIS
Saratoga, CA 95070
Cell: 408-***-****
PROFILE
** ***** ** ********* ********** as a software architect/developer in
multiple NP-complete CAD algorithms in the ASIC IC design flow; Grounds-up
design and development of high capacity software systems with fast turn-
around-time involving distributed multi-processing and multi-language
modules (C/C++ Tcl, J2EE, Java FLASH 4)
Major innovations in Physical Implementation of the IC ASIC Design Flow :
Physical Tool Data Flow Development: Floor-planning, Placement, Clock
synthesis, Optimization, Routing
Algorithm Development: Parallel RC Extraction; Multi-mode/Multi-
corner Timing/Power Optimization;
Database model development: Hierarchical Physical Database for
Power/Timing Design Closure
SKILLS
Algorithm development in C/C++ and Tcl; Data model development for fast
interactive GUI; GUI design Adobe FLASH 4;
Linux based distributed multi-processing in private/public networks (i.e.
Amazon EC2)
EDA tools: PrimeTime, Magma Talus, Raphael, StarRC
EXPERIENCE
2009-present: Nefelus Inc
Lead Architect: Currently working on hierarchical and parallel database
infrastructure and point tool algorithm development to implement the entire
IC flow with high degree of quality of results using a massively parallel
computing infrastructure (Amazon EC2 and corporate networks).
Developing a new innovative floor planning system implemented in Web Client
technologies enable drive highly incremental and fast design flow. It
includes, timing driven cell and block placement, physical partitioning and
Physical database subsystem
Delivered an Hierarchical optimization system that can enable a socket
based message passing system that updates hierarchical blocks in a main
process and individual blocks in slave processes concurrently. The
information that is communicated is in internal DB format, Tcl commands
and/or PrimeTime commands.
2008-2009: Magma Design Automation
Senior Software Architect: Delivered an alpha-level module on Talus that
performed concurrent multi-mode multi-corner timing optimization within the
signoff flow. This module used sophisticated optimization algorithms that
access incrementally and concurrently timing information from 3rd party
timing analysis engines run in parallel on multiple CPUs in the network
while being continuously updated with any design changes.
2003-2008: Athena Design Systems Inc.
Lead Architect: Lead a multi-disciplined engineer team to deliver the
flagship product Milos, built on an innovative and uncommon proprietary
distributed parallel computing infrastructure with plug-ins to 3rd party
big EDA vendor tools that has been successfully evaluated by 2 customers
and found extremely competitive.
Milos is multi-mode multi-corner timing optimization tool invoked in
the final post-route sign-off stage of an ASIC IC; It improves chip
performance, eliminates hold time violations, and reduces leakage
power in all process/temperature/voltage corners, multiple cell
libraries and functional modes at the same time; Milos uses
sophisticated optimization algorithms that access incrementally and
concurrently timing information from timing analysis engines (such as
PrimeTime) run in parallel on multiple CPUs in the network while being
continuously updated with any design changes.
Point tool Developer: Authored a fast, high capacity and accurate parasitic
extraction engine to be used both as stand alone and as embedded and
incremental for physical optimization and a "design tiling" scheme to
accelerate TAT of existing 3rd party extraction tools:
DFM-aware Parasitic Extraction tool using layout pattern based
physical modeling and calibration from industry's standard 3D field
solver tool Raphael; Reads standard format files LEF/DEF and process
parameters and outputs one or more SPEF files; Accuracy measured to be
same or better with industry standard sign-off tools while turn-around-
time is 3x faster on a single CPU; in a distributed parallel mode, can
extract 5 million nets (or 20 million gates) in 45mins using 9 CPUs on
3 process corners compared with 3.5 hours single CPU execution.
Architected Innovative technologies: incremental and stream-able physical
design data base, incremental and compact parasitics data model,
incremental extraction, unified distributed parallel programming model and
plug-in architecture for 3rd party tools, sophisticated multi-constrained
optimization algorithms, objected oriented Tcl interface to C++ objects.
1999-2003: Ammocore Technology Inc.
Co-founder and Sr. Architect: Lead a small R&D team to implement the
architecture of a both a high capacity physical IC design infrastructure
and a core point-tool application, Parasitic Extraction, essential for
analyzing chip performance before manufacturing.
Designed and implemented the layout infrastructure for the Physical
Implementation tool FabrixTM to be used as a fast search engine on
massively layout objects manipulated by GUI functions, Global router,
Placement, Extraction, DRC, Pin and Layout Abstraction.
Authored and implemented an RC extraction tool as accurate as leading
vendor extraction tools but 7X faster. It interfaces with existing
layout systems with standard formats and drives leading edge Cross-
talk Analysis tools.
Architected and managed a distributed parallel computing
infrastructure that integrates CPUs, Network resources, EDA tools and
licenses, and user errors and logs. This infrastructure was the power
behind accelerating the physical implementation of large ASIC chips 10-
15x over existing layout flows. Distributing computing in the physical
implementation space in EDA was first attempted at Ammocore.
1996-1999: Cadence Design Systems Inc.
Architect -(Promoted thru a formal process): Build and led the development
team that delivered industry's highest capacity and speed extraction tool,
HypeExtractTM. The tool is used in production by several major ASIC
suppliers, and became an integral part of the Silicon EnsembleTM product
family. Developed the next generation multi processing capabilities for
large scale computing of multi million gate ICs. Worked closely with major
accounts to bring the product to maturity and in a fully automated
production environment. Delivered superior physical analysis capabilities,
which were key for proliferating the product into the ASIC market as part
of the design kits supplied by their foundries.
1994-1996: High Level Design Systems (Subsequently acquired by Cadence)
Senior Member of Technical Staff: Chief Architect and developer of
industry's next generation extraction technology. The technology extracts
critical parameters for multi million gate complex ICs used by analysis
tools to produce chips that are faster, smaller, and consume less power.
The technology provided for a quantum leap in speed and capacity, unmatched
by prior products in this space. With its state-of-the-art geometrical
search and memory management algorithms, the tool's processing capability
was as much as 8X faster than predecessors.
1991-1994: National Semiconductor
Circuit Designer, LAN Division: Developed a design flow methodology from
synthesis to layout that incorporated proprietary Delay Calculation,
Extraction, and other tools, as part of National's NaDEA pilot program that
was introduced during the migration into 0.35?m manufacturing process.
Software Engineer, CAD Division: Developed Delay Calculation (NEWTON) and
Physical Analysis tools that were used in production by National's IC
design centers worldwide.
1990: IBM Corporation, Rochester MN
Design Automation Engineer: Developed Test Pattern Generation tools that
were incorporated into the CAD framework used by IBM's IC design community.
Co-author of 2 patents while at Ammocore and 1 patent while in Athena
Design, all three on "partitioning for multi-processing"
EDUCATION
Master in Business Administration, 1994 : San Jose State University, San
Jose, CA
M.S. in Electrical and Computer Engineering, 1985 :George-Mason University,
Fairfax, VA, GPA 4.0
B.S. in Computer Engineering and Information Science, 1982 : University of
Patras, Greece, GPA 7.7/10
OTHER ACCOMPLISHMENTS
Two years of post graduate research in Electrical and Computer Engineering
at George-Mason University, Fairfax, VA. Published two papers on RISC
architectures and super computing.
2 years of post graduate research in Electrical and Computer Engineering
the University of Wisconsin, Madison, (passed PH.D. Qualifying exams)
focusing on CAD algorithms.
HOBBIES
Mountaineering, soccer, wood working,music.
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