Design Project

OBJECTIVE

Seeking a relevant position at a semiconductor organization to contribute

to the growth of the company with my technical and communication skills and

enhance my skill set simultaneously

EDUCATION

University at Buffalo, NY

Master of Science, June 2010

Major: Electrical Engineering

GPA: 3.7/4.0

Osmania University, India

Bachelor of Engineering, May 2008

Major: Electronics & Communication Engineering

First class with distinction

STRENGTHS

- Digital Circuit Design - ASIC Design Flow

- Static Timing Analysis

- Analog Circuit Design - FPGA Implementation

- VLSI Testing

- Computer Architecture - Verilog RTL Design

- Digital & Analog IC Layout

- Integrated Sensor Systems - VLSI Device Physics

- Digital Signal Processing

ACADEMIC EXPERIENCE

RESEARCH ASSISTANT, Professor- Adly T.Fam

Dec 2009 - May2010

. Focused on different ADC architectures and Designed a novel

Analog to Digital Converter which utilizes the advantages of

Flash and integrating type architectures

PROJECTS

HARDWARE IMPLEMENTATION OF 8 POINT DCT USING DISTRIBUTED ARITHMETIC

. Focused on different algorithmic implementations of DCT

. Implemented DCT with Distributed Arithmetic technique for its

speed and efficiency

. Used Xilinx Design Suite ISE for Verilog RTL coding and ModelSim

for simulation

. Implemented the design on FPGA (BASYS BOARD - Digilent, Inc.)

and tested it for its accuracy

DIGITAL PHASE LOCKED LOOP

. Implemented low- power and high speed logic circuits in the

design using AMI 0.6 micron technology

. Project involved schematic and layout of of Phase Frequency

Detector, Charge Pump, Loop filter and

Voltage Controlled Oscillator

. Implemented Voltage Controlled Oscillator in both single ended

and differential configuration

. Accomplished lock time of 10 microseconds for a clock frequency

of 20 MHz

8-BIT SLOPE INTEGRATING ANALOG TO DIGITAL CONVERTER

. Project involved schematic design of sample and hold, 8 bit

counter, comparator, integrator and control logic that resets

the system for the next sample

. Design is successfully simulated at a speed of 20 KHz

32-BIT PSEUDO RANDOM PATTERN GENERATOR (PRPG) USING VERILOG HDL

. Project includes design of test vector generator system that

generates 32 bit pseudo random test vectors which is implemented

using LFSR

. Implemented code both in structural and behavioral modeling

. Simulation is performed in NC-verilog

TESTING OF 8-BIT ALU USING NI-ELVIS HARDWARE AND LABVIEW

. Multiple functions of ALU were tested using DSP based tester instrument

NI-ELVIS and Lab view

8-BITSEQUENTIAL BINARY MULTIPLIER

. Used Xilinx Design Suite ISE for Verilog RTL coding and ModelSim

for simulation

. Designed datapath and its controller using ASMD chart

GLARE SENSOR ARRAY CHIP

. Designed a pixel which detects and estimates the glare based on

user defined threshold

. Laid out 10 X 10 pixel array using Magic7 tool with AMI 0.6 micron

technology and simulated with SPICE BSIM-3 model parameters

FOLDED CASCODE OPERATIONAL AMPLIFIER (OP-AMP)

. Focused on the matched layout of the op-amp where all the

transistors were designed and laid out based on the common

centroid rules for MOS transistor matching using AMI 1.5 micron

technology

. Laid out using Cadence Virtuoso tool & simulated using SpectreS

Level-1 model parameters

. Achieved a gain of 90dB, slew rate of 9.5V/?s, gain frequency

of 20MHz and power dissipation of less than 3mW

DESIGN OF HIGH GAIN PRE AMPLIFIER CHIP FOR SENSOR

. Project involved schematic and layout of preamplifier circuit

for a sensor signal

. Designed a digitizer circuit to convert sinusoidal wave to

digital pulse signal

. Verified Power Dissipation, Loop gain, CMRR, Gain Bandwidth

Product and Frequency Response

TECHNICAL SKILLS

Tools :

Cadence-Virtuoso & NC-Verilog, Xilinx ISE

Mentor Graphics Modelsim, Magic

Programming Languages : C, C++, Perl, Spice3

Hardware Descriptive Languages : VHDL, Verilog

Simulation Packages : MATLAB, Labview

Operating Systems : Windows 95 and

later versions, Linux

Equipment : Network

Analyzer, Spectrum Analyzer, Oscilloscope,

Signal Generator

CAMPUS INVOLVEMENTS

. Presented a poster of CMOS vs. CCD devices at Poster competition

at EE Dept., University at Buffalo

. Webmaster, Graduate Student Association

. Volunteer for GSA Elections 2009 & 2010, GSA Sponsored games and

Senate meetings

. Tutor for Math and Physics to Freshman, Juniors and Sophomores

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