Engineer Design

GALIB SAMDANI

E-mail: *****.*******@***.***

949-***-****(Cell)

SUMMARY

ASIC Design Engineer with diverse experience in the area of ASIC/SOC,

seeking a dynamic position in the area of ASIC design/verification/testing.

. With 10+ years of experience involved in different aspects of ASIC/SOC

development: Specification, Design, Pre-Si validation, Post-Si SV

debug support, synthesis, timing analysis, Reliability analysis, ECO

methodologies, Performance Analysis, Power Management.

. Experienced in high Speed IO (PCI Express) layers (Phy, Link,

Transaction layers), DMA, Hardware Virtualization, DFT(Design For

Testing) Architecture, JTAG interface, Memory Controller protocols,

Computer Architecture, Memory Systems, Cache Architecture.

. Design experience of various high-speed industry standard IO, memory,

cache coherency micro-architecture for multi-processor based systems

which include memory controller, DMA TOE engine, Packet Processor, IO

controller, and interconnect technologies that includes PCI-Express

and involves Data-path, Control Path, State Machines, Bus Arbiters, In

Order Queue, Out of Order Queue, Error detection and Correction, LFSR,

BIST logics design etc.

. Excellent understanding of design methodologies and design for test

(DFT), Signal Integrity issues.

. Practical working experience in projects using various Software and

Tools, such as, Verilog, System Verilog, Prime Time for Static Timing

Analysis(STA), Questa-Sim, VCS, Modelsim, Open Verification

Methodology (OVM), VHDL, C, C++, Specman, Debussy, Synopsys DC

scripting, PERL/TCL and other scripting languages, Databases, SQL

Query Languages.

. Familiar with digital signal processing (DSP) technology that includes

digital filter functions.

. Good understanding of Compiler, Device Drivers and OS internals.

PROFESSIONAL EXPERIENCE

Senior Design Validation Engineer

2007 - 2010

Intel Corporation, Irvine, CA

Responsibilities include working as a key person in Silicon validation team

with emphasis on DFT architecture validation. In this process developed

comprehensive test plans based on the Component Specification, developed

the test bench and tracker/checker architecture and sequences using OVM

methodologies. In this role played as the key stake holder in Architectural

Bug analysis, validation of the multiple DFX features ( MEMBIST, IBIST,

ACIO Loopback, JTAG BSCAN, DDR3 timing protocols etc.), Performance

Bottleneck Analysis, and aiding the Post Si SV team in root causing and

closure of any Si issues, suggesting work-around solution if a particular

issue is not going to be fixed in the respective stepping of the Si.

Senior Component Design Engineer, Intel Corporation

2000 - 2007

Worked as a senior Digital Design Engineer with the Silicon Design team

providing Micro-architecture solutions for the complex component

specifications, micro-architecture design/validation to meet the component

specification and defined protocol standards. In this process covered the

following tasks

. Responsible for all phases of the design process including: RTL design,

simulation of VHDL/Verilog based model, Gate Level Simulation (GLS),

Static Timing Analysis(STA) using Prime-Time, RTL optimizations to meet

timing, ECOs, Reliability Verification (RV), Performance Analysis.

. Led the DMA cluster design team.

. Developed the RTL code for the production of Intel chipsets for Memory

Controller/IO Controller used in Server/Workstation platforms.

. Designed individual clusters such as PCI-Express Packet Processor,

Virtual Address translation Block,

Decoder/Encoder, Cache controller block, DMA TOE engine, In-Order and Out-

of-Order Transaction Queue blocks etc.

. Maintained and changed the design with the updated feature

specifications.

. Provided Post Silicon System Validation support.

. Provided Chip Performance Analysis metrics, evaluated bottleneck points

and reported the analysis data.

. Provided Test Plan, Test Vector debug and support, managed small group

dedicated to specific test plan execution etc.

Research Assistant

1994 - 2000

University of Arkansas, Fayetteville

Research Projects

. Designed and implemented a performance driven Data Cache and Stream Cache

Architecture based on differing types of data locality.

. Designed and implemented a Processor in Memory (PIM) Computer

Architecture to attain better memory access bandwidth (Funded by ASTA).

. Designed and constructed close-space sublimation systems for the

deposition of CdTe thin films (Funded by NASA/EPSCOR).

Equipment Experience

Digital Storage Oscilloscope

Logic Analyzer

Spectrum Analyzer

Scanning Electron Microscope (SEM).

EDUCATION

Ph.D., Computer Systems Engineering, University of Arkansas.

MS, Electrical Engineering, University of Arkansas.

AFFILIATIONS

Member IEEE & IEEE Computer Society, USA

Active member of the IEEE Computer Society, Orange County Chapter

CITIZENSHIP

USA

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