Engineer Design

IONEL ADAM

Str. G-ral. Ion Cernatescu, Bl. A**, Sc. 1, Apt. 18

Craiova, ROMANIA

Cell: +40-788-******

E-mail: *****.****@*********.***

Objective:

- Receive a position in digital IC/DSP design engineering.

Summary:

- Background in digital IC design and Digital Signal Processing, more than

10 years;

- Verilog, Matlab and C: from mathematical model to RTL implementation;

- Verification, functional & gate-level simulations using ModelSim and VCS;

- Some SystemVerilog exposure (RTL & simulation).

- Area/speed code optimization, low-power design;

- Synthesis, Place & Route and Timing Analysis using Xilinx FPGA devices;

- Working knowledge of: digital filters & equalizers (FIR, FFE, DFE),

FFT/IFFT, error correction (Viterbi, Reed-Solomon), H.264 video

compression;

- ASIC experience - synthesis using Synopsys and Mentor Graphics tools;

Most used Tools:

-Modelsim, Synopsys DC & VCS, MATLAB, Xilix ISE, LeonardoSpectrum,

Octave, Visual C++.

Education:

MSEE

(equivalent title for 5 years full length courses)

University of Craiova, Romania

Electromechanics Faculty 1988-1993

Work status: visa and work permit required outside Romania

(former US H1-B visa holder).

Experience Employment:

1. Mar. 2008 - present: Movidius Ltd (Ireland), Timisoara office -

Romania

Title: senior digital IC design engineer

Project: Multi Processor SOC blocks:

- H.264 CAVLC encoder/decoder

- FFT core for GPS satellite correlator,

- MPEG-2 transport stream (Reed-Solomon Codec, Interleavers, Conditional

Access),

- DVB Viterbi Decoder C model,

- FP16 Quadratic Interpolator (sine/cos/atan/exp/log/rcp functions for

OpenGL HW acceleration),

- FP32/16 SIMD adders.

Role:

- Algorithm implementation in Matlab or C, Verilog coding and debugging,

Modelsim and VCS simulations, ASIC synthesis, area/time/low-power

optimization.

Tools: Synopsys VCS & DC, ModelSim, Matlab & Octave, Visual C++ 2008.

2. Jan. 2003 - Mar 2008: ICS Design SRL, Craiova - Romania

Title: digital IC design engineer

Projects:

- FP32 adders and multipliers,

- Gigabit Ethernet Viterbi Decoder C model,

- WLAN Viterbi Decoder,

- Viterbi Decoder IP core,

- CORDIC IP core & Matlab toolbox,

- Complex LMS Adaptive Equalizer & Matlab toolbox,

- FIR Filter IP core & Matlab toolbox,

- Signed Multiplier IP core & Matlab toolbox,

- Additive White Gaussian Noise Generator.

Role: - Algorithm implementation in Matlab or C, Matlab GUI developing,

Verilog RTL & testbench code generator, Verilog coding and debugging,

Modelsim functional & gate level simulations, PLI user tasks, FPGA

synthesis and place & route (Virtex II device).

Tools: Matlab, Xilinx ISE, ModelSim, Visual C++.

3. Apr. 2002- Sept. 2002: TELEWISE Communications Inc, San Jose office, USA

Title: digital IC design engineer

Projects:

- 32 bits/32 MHz Master/Target PCI interface,

- 10/100 Ethernet MAC,

Role - Verilog coding and debugging, Verilog testbench and functional &

gate-level simulations,

- FPGA synthesis and place & route (Virtex E device), Timing

analysis (PCI timing constraints met)

Tools: Xilinx ISE, ModelSim.

4. Jan. 2001- Sept. 2001: MASSANA Design Ltd, Dublin office - Ireland

Title: digital design engineer

Projects:

- WLAN Viterbi Decoder, k=7, R=1/2

- Gigabit Ethernet PHY

Role: - RTL verification team member, debugging of Verilog code,

- functional simulations of different modules using ModelSim .

Tools: ModelSim, Verilint, Synopsys Design Compiler.

Training course: "Synthesis Methodology Workshop - Esperan ", Aug. 2001

5. Jun. 2000- Oct. 2000: Red Line Communications Ltd (Canada) - Romania

branch

Title: digital design engineer (part time)

Project: 32-bit PCI master interface for an ADSL modem

Role: VHDL coding and debugging, synthesis and place & route (Xilinx

VIRTEX FPGA device).

Tools: Xilinx Foundation 2.1, LeonardoSpectrum.

6. Nov. 1998-Nov. 2000: DAEWOO Information Systems Romania SA - Hardware

engineer

7. Aug. 1995-Oct.1998: Comrace Computers SRL - Hardware engineer

8. Mar.1994-Mar.1995: Pop Service Electronic SRL- Electronics engineer

Projects (discrete components based design) such as:

- Industrial data acquisition system (PC 8-bit ISA cards and analog

sensors);

- 20 MHz digital oscilloscope ISA card (with TLC5510A ADC, 2048x9 bits

FIFO);

- Overheat protection for motor bearings, switched power supply

Role: - design of low-level schematics, bill of materials,

- testing, setting and repairing modules, verifying PCB layout.

Tools: OrCAD.

Contact this candidate