J. Luis Santisteban
San Diego, CA, ***** - 858-***-****
ablyem@r.postjobfree.com
http://www.linkedin.com/in/luissantisteban
http://luissantisteban.webs.com/
Summary
Experienced and accomplished electronics engineer with broad technical
knowledge, skill, and experience in the design, debug, verification, and
integration of complex digital communication equipment. Extensive
expertise in detailed electronic circuit design and the management of
multidisciplinary engineering projects. Detail oriented and team oriented
with exceptional problem solving skills.
Professional Experience
Principal Engineer/Manager - L-3 COMMUNICATIONS, TELEMETRY WEST
San Diego, CA June 2004 -
March 2009
Created the process, structure, and budget to manage a new sustaining
engineering section that drives all hardware sustaining engineering
activities for airborne, space, and ground telemetry product lines used in
military missile and aircraft testing. Managed two direct reports and
numerous other project personnel throughout the company.
Created, planned, and managed a $900K+ annual labor budget that funded
numerous matrix multidisciplinary sustaining engineering projects using MS
Project and Earned Value methodology
Personally analyzed and corrected numerous long-standing hardware,
firmware, and software design flaws in existing products
Redesigned several board assemblies with Analog Devices DSPs and large
FPGAs using Xilinx ISE (VHDL), Altera MaxPlus, OrCad, PADS, ModelSim,
Pspice, Simplify, AutoCAD, Viewlogic, and numerous other development tools
and environments
Created a large comprehensive test plan under a severe time constraint for
a new space encryption system based on several incomplete and incoherent
test plans
Investigated, analyzed, and restructured numerous broken processes
eliminating unnecessary and recurring waste of engineering labor by
$192K/year while improving the efficiency of necessary processes
Reduced unnecessary ECO activity 80% by institutionalizing sound change
management criteria
Initiated, planned, and managed the development of a sophisticated Excel-
based product configuration tool that generates detailed parts lists and
parametric test cases from top level system options
Resolved hundreds of obsolete parts by properly qualifying alternates and
initiated a new proactive company-wide process to identify and manage
obsolete parts issues
Staff Engineer - ERICSSON
San Diego, CA May 1999 -
March 2003
Performed design and integration engineering of new CDMA cellular base
stations.
Designed the low noise digital circuitry for a multi-mode CDMA receiver
card with first pass success
Specified and oversaw the design and fabrication of two 20-slot 24-layer
digital backplanes used in a high capacity CDMA base station with first
pass success. Successfully planned and executed backplane DVT.
Developed the critical internal high speed differential communication
interfaces for a high capacity CDMA base station which required impedance
matching across multiple cables, distribution panels, and expansion chassis
- developed and modeled a simple passive transformer solution that avoided
a problematic active buffering solution
Planned and executed the system level integration DVT of the high capacity
CDMA base station - was a key contributor of the initial HW/SW integration
of prototype base station chassis
Developed and executed a realistic accelerated life cycle test of large
FPGA column grid arrays use on the high capacity base station CDMA cards
Upgraded and performed DVT of PowerPC card components to operate over the
industrial temperature range - adapted a production card tester for
supporting the DVT
Debugged a corrupt calibration data problem on deployed CDMA base stations
for the Salt Lake City Quest network during acceptance testing ahead of the
2001 Winter Olympics. Developed the procedure to correct the flaw and
directed the successful correction of the problem in the field on over 150
cell sites
Staff Engineer - QUALCOMM
San Diego, CA June 1996 -
May 1999
Performed system integration and sustaining engineering of CDMA cellular
base stations with the responsibility and authority to analyze and approve
all changes to base station systems (HW, SW, RF, Mechanical)
Planned and implemented multidisciplinary performance improvements and cost
reduction changes to multiple base station models
Planned and directed new product introduction (NPI) of hardware from
engineering to production
Planned and directed complex field upgrades and design corrections of base
station networks
Wrote hundreds of ECOs to resolve every dependencies and convert the CDMA
base station product line documentation to a new CM product structure
Performed numerous staff assignments to solve a wide variety of difficult
and urgent problems by supplementing project staff and heading special task
forces
Lead Engineer - DATAMAX Inc. and COMPUTER SCIENCES CORPORATION
NASA Dryden Flight Research Center, Edwards, CA
February 1988 - June 1996
Performed project engineering and detailed circuit design for a contractor
HW engineering team at the NASA Western Aeronautical Test Range.
Planned, scheduled, and directed the detailed design of a multi-ported
shared memory network consisting of six complex board assemblies and high
speed optical links for real-time telemetry data distribution using
TimeLine scheduling SW and Earned Value methodology
Specified a new networked hardware development environment including the
selection of desktop workstations, central data server, IP network, and
application SW for a team of five digital design engineers.
Performed detailed design of several new FPGAs and board assemblies for VME
and ISA multi-ported memory boards and wrote HW diagnostic SW in assembler
and C
Successfully planned and directed the installation, configuration, and
integration of the custom real-time shared memory network
Developed and executed the plan to make the Dryden telemetry data securely
available over the NASA global satellite communications network
Directed and performed numerous other integration tasks within and between
NASA facilities to meet Dryden mission requirements
MTS IV - GOULD Inc. and SYSTEMS ENGINEERING LABORATORIES
Fort Lauderdale, FL January 1980
- January 1988
Planned, scheduled, and directed the detailed design of a multi-card front-
end communications I/O subsystem for a series of proprietary real-time mini-
supercomputers running Unix and real-time operating systems - Performed
detailed design of all cards of the I/O subsystem - took control of a
failing VME I/O subsystem development project and successfully planned and
executed completion. Performed detail design of dozens of other I/O and
communications cards - Wrote HW diagnostic SW in C and assembler.
Education
SDSU Extended Studies Department, 10 week Leadership training
Broward County Community College, Ft. Lauderdale, FL - 40 units towards a
BS degree
Control Data Institute, Coral Gables, FL - Computer Technology
Other
U.S. Military Veteran
Active Secret Clearance
Speak, Read, and Write fluent Spanish