Design Engineer
Resume:
Confidential Resume
Sharad Desai
San Jose
CA 95138
Objective: Seeking a challenging position in ASIC or FPGA design or
verification.
Contributed to tape out of 7 Asics. Expertise in RTL design and
verification using VCS, NCSIM, and Modelsim simulators.
Programming languages used are Verilog 2001, VHDL, Vera, and SystemVerilog.
Also used C, C++, Perl, Make, CVS,
LSF and Shell Scripts. Processors used are Intel, IBM Power PC, and ARM.
Verified PCIe, Hyper Transport, PCI,
AMBA Bus and other standard buses. Vendor tools from Cadence, Synopsys DC
and DC-topo, Modelsim, ISE,
Synplicity, and Debussy. Designed MAC layer for 802.11abg systems
PROFESSIONAL EXPERIENCE:
Consulting services for Altera, Cisco Systems, Sun Microsystems, Sony Corp.
LTX, Advansys, SGS Thompson,
Silicon Graphics, and Skipper wireless. Services provided are RTL design,
synthesis and verification and FPGA-to-ASIC conversion.
Asic Consulting Services : (June'09 - Mar'10):
. Responsible for design and verification of proprietary DMA controller..
Also contribute to the project scheduling, system documentation etc.
Leadis Technology: Staff Design and Verification Engineer (May '07 -
Mar'09) :
. Design and developed SOC Audio codec. Responsible for design of sub block
using AC97 and I2C interfaces. Xilinx FPGA
development and verification. Simulated Audio Codec RTL with Matlab DSP
algorithm into ASIC.
Performed synthesized using Synopsys DC and Primetime. Also performed
verification at gate level, worst and best case simulations after place and
route. FPGA was implemented to verify audio filter implementation.
Responsible for RTL coding in verilog, Synthesis, Primetime, Clock Tree
Insertion, Scan Insertion, DRC and post timing analysis using Cadence's
tools.
Netlogic: Consultant (Feb.'07 -May'07): Worked as a contractor for Layer7
packet processing company.
Module verification of Hyper Transport interface. Test bench environment
creation.
Generated regression tests and created tests to verify RTL.
Skipper Wireless: (Sept '05 - Jan '07)
Designed MAXIM radio interface for frequency synthesizer for 802.11a/b/g
Lead FPGA verification and subsequent,
tape out of LSI LOGIC's RAPIID chip. Xilinx, LSI Logic tools and MODELSIM,
mixed mode Verilog and
VHDL IP, simulator was used together with C and Verilog. Responsible for
design and verification, and bring up of fpga and asic.
Credence : Consultant (June'05 - Sept.05)
DDR2 Memory Controller IP FPGA implementation and verification using
Altera and VCS .
This module was part of larger tester system.
Beceem Communications Inc.: Consultant (Jan'05 - May'05)
Created test bench environment for verification of 802.16 PHY. Generated
test cases and verified that the
rtl complies with MATLAB reference model. Responsible for setting up
verification environment supported for module
and system level verification.
Texas Instrument: Consultant(Oct'04 - Jan'05):
Verified at block level modules and created multiple tests for it. Also ran
Spyglass for synthesis analysis.
and used code coverage tool for the design. Synopsys VCS simulator was
used . Also supported DFT
analysis for the wireless Asic.
Microsoft Corp.: Consultant (May '04 - Sept.'04):
Participated in verification of PCIe south bridge for Xbox project.
Using existing testbench environment of VHDL, Verilog and Modelsim
verified South bridge. Verified PCIe initialization state machine(LTSSM).
Coding of tests and design verification of proprietary IPs.
Intel: Chandler Az. Consultant( Feb'04 - May'04):
Verification of peripherals using Perl generated tests.
ASIC Consulting Sevices: San Jose (Oct.'02 - Nov.'2004)
Development of IPs, including rtl, synthesis and verification for FPGA and
ASICs.
Creation of test benches and monitors in Perl, Csh, and Verilog and design
and board bring up.
Principal Engineer : Bermai Corp, Palo Alto (Feb'02 - Sep.'02)
Contributed to first-pass silicon for MAC ASIC for WI-FI 802.11a.
synthesis and simulated with baseband.
Responsible for block definition, RTL (verilog) coding and verification,
using VCS and PLI on Linux system.
Also generated test plan, test benches and implementation of PCI design
and verification. This ASIC interfaced with PCI
and PHY. Developed test suites, random and directed test cases. Generated
code coverage report using Synopsys.
MTS: Luminous Networks: ( Mar. '00 -Dec. '01) :
Responsible for design synthesis and verification of Gigabit Ethernet MAC
to be used in 802.17 application.
Also lead a team of engineers in FPGA and synthesis and verification of
Traffic Shaper Queue Management .
VERA was used for verification. Created a test plan and test environment
for VCS simulation .Created many directed
and random tests. This was 0.18u design and closed to 1M gates. Also
Verified token bucket algorithm for
traffic shaper FPGA Also involved in MII and SDRAM simulations.
Consultant @ Sun Microsystems:(Oct'99 -Mar.'00)
Responsible for verification of proprietary graphic processor bus and
checking of correct operation of
FIFOs in the design. This Asic contained close to 2M gate CMOS ASIC.
Consultant @LTX and Advansys Corp.( Aug.'98-Aug.'99)
Participated in the design of memory controller for SRAM for high speed
tester. Created test benches
for functional digital logic verification using Verilog-XL and synthesis
using Synopsys.
Also worked on PCI to Sbus interface as a part of DMA engine and verified
the design in HW/SW
co-simulation. Generated Memory,BIST,and Functional test vectors for LSI
Logic prior to chip release.
Consultant @ Cisco Systems: (June'06-July'97)
Successfully verified the design of SDRAM controller using Denali and
Verilog models, network Asics,
at RTL and Gate Level. This was part of a CAT5K product. Also verified up
down link ASIC at RTL and Gate Level
simulations. Worked with a team of engineers for 700k router ASIC. Verified
module level interface,
wrote protocol monitors and created test plan for Asics.
Education: Certificate in VLSI Design Engineering @ University of
California Santa Cruz
BSEE (Hons.) The City University (London, England)
Courses:
.SystemVerilog for Advanced Design Verification @ UC Santa Cruz
.Advanced ASIC Physical Design @ UC Santa Cruz (Project: 10GE
Mac)
. RTL2GDSII @ UC Santa Cruz
. Synopsys VERA, Prime Time and Design Compiler Training
. Introduction to TCP/IP and data Communications and Networking
. Computer Architecture and IC Fabrication through Stanford
. Sonet and ATM Class at UCSC
. LSI LOGIC and Toshiba Design training
. Mentor Calibre Training Class
SYSTEM & LANGUAGES:
CAD TOOLS:
VHDL, Verilog using SYNOPSYS and Mentor Graphics and Model
Technology.
LSI LGIC, ALTERA, Xilinx, C, C++, PERL, Make, CVS, RCS, and
LSF.
SYSTEMS: LINUX, SUN Solaris, and Windows
Misc: US Citizen; References available upon request.
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