Engineer Electrical Engineering

ANEESA KUNJU

Cell: 1-408-***-****

Email: ***********@*****.***

OBJECTIVE

Seeking a challenging position in the area of Software QA, with varied responsibilities, and which will expand my knowledge and skills.

PROFILE

* Solid understanding of black box, white box, unit, performance, stress, regression, client/server testing, manual and automated testing.

* Strong experience in studying and analyzing functional specifications, writing test plans and test cases using Selenium, JUnit and QTP and implementing test cases.

* Hard-working team player and quick learner with strong analytical and communication skills.

* Knowledge of all phases of Software Development Life Cycle (SDLC), and experience with Agile test-driven methodology.

* 3 years of Software QA experience and 7 years of Hardware Verification experience.

* US Citizen.

SKILLS

Languages: Java, C++, Perl, Assembly, JavaScript, HTML, XML, SOAP, SQL,

Vera, Verilog.

Database Systems: MySQL, MS Excel.

Testing tools: Selenium IDE, Selenium RC, JUnit, QuickTest Pro (QTP),

Mercury Quality Center

OS: Windows, Unix.

Other tools: Eclipse, Clearcase, Perforce, Bugzilla, Jira.

EDUCATION

MS in Electrical Engineering - Wright State University (2000)

BS in Electrical Engineering - Purdue University (1995)

EXPERIENCE (10 years)

Career Element (7/10 – present, part-time)

QA Engineer:

-Performing intensive Manual and Automation testing using Selenium IDE and Selenium RC for a multi-tiered web application.

-Writing unit tests with JUnit.

Redback Networks (Ericsson) (4/08 – present)

QA Engineer:

-Sanity Test Retriever Web Application:

-Performed Manual and Automation testing using Selenium IDE, Selenium RC, JUnit and Java for a web application backed by a MySQL database, by creating test plans, test cases and test scripts in Selenium to automate a web application’s functionalities.

-Testing included Client-side GUI testing and cross-browser testing.

-Designed Selenium smoke, sanity, acceptance, functional and regression test cases.

-Built and analyzed weekly runs, to determine the quality of integration branches.

-Analyzed smoke and sanity tests in various environments to confirm stability of the code.

Hardware Verification Engineer (4/05 – 4/08):

Verified functionality of a packet processor execution unit by:

-Writing and maintaining a reference model in C++ for the execution unit.

-Writing and maintaining a monitor in Verilog to compare RTL design against reference model, and report discrepancies.

-Writing a random instruction generator in C++ to generate random tests to verify the execution unit.

-Writing directed tests in Assembly to verify the functionality of the execution unit. These cover functionality like memory operations, local scratchpad operations, branch operations, and error and interrupt handling.

-Wrote multi-threaded tests in Assembly to verify the functionality of a multi-threaded execution unit.

Intel Corporation (10/04 -3/05)

ASIC Verification Engineer (Processor Group):

-Using C++ to write checkers to verify processor functionality.

-Wrote checker for Tap controller and Scan controller.

-Wrote testplan, implemented testplan and debugged RTL for Tap Controller.

Sun Microsystems (8/01 - 8/04)

ASIC Verification Engineer (UltraSPARC Processor Group):

UltraSparc IIIi Processor:

-Writing diags in Assembly for verifying UltraSparc processor functionality.

-Wrote testplan to cover functionality of the JBU

- JBUS Interface Unit in a processor.

This block included the Transaction Issue Unit, Outstanding Read Queue, Snoop Queue and Error Control and Status Register. Implemented testplan by writing directed diags in Assembly to ensure correct protocol, data consistency and coherency.

-Writing monitors in Verilog to monitor processor/ASIC behavior and writing diags to verify monitor functionality.

-Random regressions : Ran and maintained random generators, and debugged diag failures to see if there were bugs. Tweaked environment by changing instruction weight files and modes to reproduce system bugs successfully and cover chip functionality.

Post Silicon Debug:

-Responsible for test vectors and silicon debug of processors.

-Writing Perl and C-Shell scripts to help in environment debugging, testvector generation and making datalogs from tester more debug-friendly.

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