Engineer Design

Fazela M. Vohra

**** ********* ******, **********, ** - 60194 ? 214-***-**** ?

******@*****.***

Summary

To obtain a position as an Engineer to utilize my strong analytical

aptitude, attention to details and problem solving skills to be an agent of

change and innovation. Successfully completed many projects during 3+ years

as a Design Engineer and simultaneously pursuing my second Masters degree

in Engineering Management.

Education

. Masters in Engineering Management

Present

Santa Clara University, CA

. Certificate in Project Management (4.0/4.0)

Sep 2009

California State East Bay University, CA

. Masters in Computer Engineering (3.8/4.0)

Aug 2006

Southern Methodist University, TX

. Bachelors in Electronics Engineering (3.7/4.0)

Jun 2003

Mumbai University, India

Work Experience

Intel Corporation - Santa Clara, CA

Aug 2006 - Present

Design Engineer, Standard Cell Library Development

. Led teams for designing and characterizing standard cell library

blocks under different operating conditions to generate detailed

specifications for circuits.

. Conducted testing and debugging of circuits to improve speed, area and

power to meet customer requirements at circuit and layout level.

. Facilitated integration, library releases and post-release support for

multiple customers.

. Developed numerous scripts to increase automation, ease design and

characterization via TCL and Shell scripting.

. Researched new CMOS device features by extensive modeling and

simulation for 45, 32 and smaller nanometer technologies.

STX Cadware Inc. - Irving, TX

Jun 2005 - Sep 2005

Junior Developer Intern

. Implemented physical layout automation flows using SKILL for different

sized functional blocks.

. Automated the process of CDK (Cadence Design Kit) comparison by

creating and simulating schematics, generating layouts using

VirtuosoXL, running extraction and simulation of layouts for

verification.

. Programmed a GUI interface for CDK comparison to generate user-

friendly reports and increase operational efficiency.

Texas Instruments Inc. - Dallas, TX

Jan 2005 - Jun 2005

Test Engineer Intern

. Benchmarked and tested multiple usage scenarios for 1710 H3 circuit

boards housing OMAP (Open Multimedia Application Platform) chips used

in Nokia phones.

. Documented 1710 H3 circuit board test procedures and results for

customer review and feedback during the design life cycle.

. Coordinated the packaging and release of the OMAP-Software products

for different teams.

Southern Methodist University, TX

Sep 2005 - Aug 2006

Research Assistant, Department of Electrical and Computer Engineering

. Research Assistant in the area of post-manufacturing defect diagnosis

and yield improvement for circuits.

. Developed a new tool to improve the efficiency of post-manufacturing

diagnosis to pinpoint faults to single manufacturing defects.

Mumbai University - Mumbai, India

May 2003 - Dec 2003

Associate Professor, Department of Computer Engineering

. Designed course work and assignments for engineering students for C

programming class.

. Planned and conducted laboratory classes for Data Communication and

Microprocessor Interfacing.

Publications

. F. Vohra, C. Zhou, P. Gui, "A Two-Pass Diagnosis Method for Accurately

Locating Logic Faults in VLSI Circuits", IEEE International Symposium

on Integrated Circuits, 2007 (ISIC 2007).

. F. Vohra, W. Jiang, M. Wang, H. Ramamurthy, "LibScaling: A Pshift

Driven Library Scaling Methodology and Flow", Intel DTTC Conference,

2009.

Coursework

. Design: Digital Logic Design, Microprocessor System Design, VLSI

Design, Computer Architecture

. Programming: Parallel and Distributed Processing, Computer Networks

and Distributed Systems, Operating Systems and System Software

. Testing and Verification: Testing of VLSI Circuits, Formal Hardware

Verification and Validation

. Laboratory experience: Semiconductor Processing, Motorola 68000

processor interfacing, Parallel Virtual Machine (PVM)

Computer Skills

. Design tools: Cadence Virtuoso Layout Editor, Cadence Spice Simulator,

Synopsys Design Compiler, Primetime, TetraMAX, Library Compiler,

Liberty NCX, Presto, Optim, IDEAL, Carmel, Genesys

. Programming Languages: C, Tool Command Language (TCL), Shell, C++,

Cadence SKILL, Perl

. Hardware Languages: Verilog, VHDL

. Operating Systems: Windows, UNIX, Linux

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