Design Physical

KHAI D. TRAN

**** ******** **.

Austin, TX **717

Mobile: 512-***-****

Email: ***********@*****.***

OBJECTIVE: Position as a physical backend designer.

SKILLS: Astro, Apollo, IC Craftsman, Silicon Ensemble, Jupiter, Hercules, StarRCXT, Primetime,

Jupiter, Saturn, SoC Encounter, Celtic, Virtuoso, Dracula, Calibre, CTE, QRC.

EXPERIENCE:

Freescale Semiconductor, Austin, TX May 2003-June 2009

Physical Backend Designer

Responsible for physical designs of CortexA8 Platform in TSMC C65 GP-LP, ARM1176 core in

C65, and several ARM926 cores in C90. Physical design include floor planning, timing driven

Place & Route, MMMC optimization, Clock Tree Synthesis, SI analysis and repair, Timing closure,

and Parasitic Extraction on CortexA8 and ARM1176 cores with low power structures using

Encounter and Calibre for DRC/LVS and DFM verification.

Completed two ARM9 cores using Astro, Primetime, and StarRCXT. Used Astro to optimized

floorplan for die size, performance, power, and routability. Performed place and route, CTS, SI

repair, timing closure, and extraction.

TriMedia Technologies, Austin, TX March 2001-Jan. 2003

Physical Backend Designer

Did physical design for four cores and two chips in .18um and .13um using CAD tool.

Responsible for the physical design of the cores, and helped design the chips.

Delivered CPU TM32V2 core 425Mhz, more than 500k standard cells using TSMC 0.13LV

process. Performed floorplanning (Astro & SOC Encounter), Place & Route, Clock Tree

Synthesis, SI repair,( Astro, AstroXtalk), Parasitic Extraction (StarRCTX), DRC/LVS(Hercules).

Custom laid out register file in TSMC 0.13um using Cadence Virtuoso.

Motorola, Austin, TX Oct. 1995-March 2001

IC Layout Designer

Chip integration MMC2103(M-CORE CPU custom microcontroller). Performed physical validation

on all modules and physical verification using Dracula. Did floorplanning, generate abstracts, and

completed place & route using IC Craftsman. Ran DRC/LVS using Dracula.

Chip integration of M-CORE RK2. Performed physical validation, floorplanning, data prep, place

& route using Block Ensemble. Ran DRC/LVS using Hercules.

Completed padring M-CORE SIKA using Apollo and Jupiter. Performed place & route.

-Completed CMOS layout of HC05, HC08, and CH12 Microprocessors, ROM, and 2Tflash

memory.

EDUCATION: A.A in Engineering Design Graphics, May 1995

Austin Community College, Austin, TX.

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