Engineer Electrical

JAVIER SAENZ

*** *. ***** ** . *******, AZ . **234 . 512-***-**** .

480-***-**** ******.*******@*****.***

PROFESSIONAL PROFILE

SENIOR FAILURE ANALYSIS ENGINEER

Goal-oriented failure analysis engineer with proven success in failure

analysis, process manufacturing and reliability for the semiconductor

industry. Expertise in Light Emission Microscopy, OBIRCH microscope,

Energy Dispersive X-Ray, electrical characterization, and physical

analysis. Keen understanding of process CMOS flows and interpreting defects

with Transmission Electron Microscopy images and Scanning Electron

Microscopy images. Demonstrated capability in assessing failure analysis

and implementing strategies and techniques, reducing cost, and improving

quality. Over 16 years experience with Scanning Electron Bean and Focus Ion

Beam Operation. Created problem solver with solid IC process, analytical,

electrical and physical experience.

Career Highlights

? Negotiated on the yearly service agreement of the Auger Scanning

Microprobe and reduced cost by 50%. [ST Microelectronics].

? Most significant technical contributor on "Spacer Etch Optimization" and

improved the 90nm HCMOS7 technology yield by 20%. [Freescale Semiconductor]

? Identified a systematic defect on HCMOS6 that led to yield increase of

22% [ Freescale Semiconductor]

? Implemented the new construction of flooring to reduce ESD and particles

entering the wafer fab. [ST Microelectronics]

Areas of Expertise

? Scanning Electron Microscopy ? Mechanical polishing ?

Light Emission Microscopy

? Focus Ion Beam ? Cross-sectioning ?

IDS5000 E-Beam

? Scanning Auger Microprobe ? Chemical Etching/Handling ? ATE

(Automated Test Equipment)

? Thermal Emission (IR) ? SRAM Bit Map FA ?

UNIX-Knights/Cadence/Camelot

? Wafer-level Reliability ? Liquid crystal analysis ?

HP 4145/4155/4156

? Package decapulation ? Powerpoint,Word,Excel ? CMOS

Processing

? Layouts/Schematics navigation ? Backside Deprocessing ? Flip

Chip Cross-sectioning

PROFESSIONAL SUMMARY

MICROCHIP TECHNOLOGY INC.

The leader in high-performance 8-bit, 16-bit, and 32-bit microcontrollers

Chandler, AZ

2006 to Present

Senior Failure Analysis Engineer

? Perform failure analysis on reliability, automotive, and commercial,

microcontrollers at the package level to determine root cause of failure.

? Evaluate customer returns and reliability failures with data logs, memory

programmers, pattern tools, assembly language programming, and generate

failure analysis reports. Familiarize with UNIX and Windows environment.

? Responsible for operating Energy Dispersive X-ray (EDX), Scanning

Electron Microscope (SEM), Light Emission Microscope (LEM), OBIRCH

Microscope, Thermal Emission (IR), ATE Teradyne tester, hp4145 parametric

tester, IDS-5000, micro-probing, function generators, oscilloscope, curve

tracer, optical microscopes, layout investigations, chemical operations

lab, and plasma de-layering techniques (RIE).

FREESCALE SEMICONDUCTOR

The leader in high-performance 8-bit, 16-bit, 32-bit microcontroller

Austin, TX 1999-2006

Senior Failure Analysis Engineer

? Served as failure analysis coordinator to all nation-wide failure

analysis laboratories to manage database and communicate top defectivity

issues to management.

Javier Saenz - Page Two

? Principal investigator for yield loss, excursion lots, SRAM bit-map

failure analysis, in-line defectivity investigations, and electrical bench

verification on in-line Test Probe failures.

? Supported Manufacturing by Pareto analysis of Unit Probe bins and bit-map

trends. Supported Device, Product, Test, and Design, to develop design for

test, and design for failure analysis.

? Engaged with technology develop teams and played critical role in new

technology transfer.

? Monitored KLA defectivity trends and detected various patterns of yield

loss, and over-lay analysis on memory structures.

? Performed SRAM bit-map analysis with Knights/Cadence to drive to X-Y

coordinates.

ST MICROELECTRONICS

High performance semiconductors

Carrollton, TX 1992 - 1999

Reliability Engineer

? Led implementation of WLR including reliability evaluation, testing, and

assessment.

? Responsible for testing the HCI, Qbd, Vbd, TDDB, transistor

characteristics, autoclave, temp-cycle, electro migration, constructional

analysis, and thermal bias stressing (TBS).

? Provided electrical-physical failure analysis support to manufacturing,

process development, process integration, and design groups.

? Key member on implementing a "Wafer-Level Reliability Program."

TEXAS INSTRUMENTS

High performance semiconductors

Dallas TX, 1986-1992

Engineering Technician

? Performed electrical characterization on transistors, diodes, capacitors,

and resistors.

? Supervised Multi-probe operators on test program loading, probe card

evaluations, and correlation evaluations.

? Responsible for diffusion, implant operation, and wet hood operation.

EDUCATION & PROFESSIONAL DEVELOPMENT

A.S. - Electronics Communication, Texas State Technical

College, Harlingen TX

HONORS & AWARDS

Technical Excellence Award - Freescale Semiconductor

Inc. Austin, TX

Bravo Award -- Freescale Semiconductor Inc. Austin,

TX

Trade Secret NO.1056 - ST Microelectronics, Phoenix,

AZ

TECHNICAL PUBLICATIONS

? "AS-Deposited Properties and Rapid Thermal Annealing Effects on Ti/TiN

Barrier Layer for AL Plug Technology (1994-V-MIC).

? "Practical Application of wafer level Reliability Control Program" (1994

Microelectronics Manufacturing Symposium).

? "Inverted T Channel FET (ITFET) -Fabrication and Characteristics of

Vertical-Horizontal, Thin body, Mult-Gate, Multi-Operation Devices, (ITFET

SRAM Bit-cell operation).

? A novel Technology for 45nm and Beyond CMOS" (IEDM 2005-Washington DC).

REFERENCES AVAILABLE UPON REQUEST

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