Design Project

*** ******** ****** # *** ***** Gothi

Phone: 323-***-****

Santa Clara, CA 95050

Email:*****@***.***

Objective: Seeking a Full Time position in Digital, Analog and Mixed-Signal

Design VLSI.

EDUCATION:

. Masters of Science, Electrical Engineering(VLSI)

May, 2010

University of Southern California, Los Angeles

. Bachelor of Technology, Electrical Engineering(Electrical Engineering)

May, 2008

Nirma Institute of Technology, Ahmedabad, India

SKILLS

Programming Languages C, Assembly (8085, 8051, MIPS), VHDL, Verilog, SystemC,

Perl

Operating Systems MS DOS, Windows 98/XP/Vista, UNIX, Solaris.

Tools & Packages PSim, Matlab, Nanosim, Cadence, EPD, HSPICE, ModelSim.

Know-how Analog circuit design and modeling, integrated circuit

design and simulation, gate level simulation with timing,

circuit optimization for low-power and high-speed digital

VLSI, knowledge of verilog and RTL design, transistor-level

analog IC design using CMOS technologies as well as

Cadence, System On Chip(SOC), Phase Locked Loops and

Frequency Synthesizers, Sampling Circuits and Comparators,

Switched Capacitor Circuits, Nyquist Analog to Digital and

Digital to Analog Converters.

Relevant Course Work

Computer System Organization, MOS VLSI Circuit Design, Power System

Protection, Analog and Non- Linear Integrated Circuit Design, VLSI System

Design,VLSI System Design II, Mixed-Signal Integrated Circuit Design,

Directed Research (Under Prof. Sandeep Gupta), Mixed-Signal Integrated

Circuit Design-II, Modern Solid State Devices.

Academic Project Experience

A Bandgap Reference Circuit in a 0.18?m CMOS Project:

Aug, 09 - Dec, 09

. Designed a bandgap reference in TSMC 0.18um technology where the

target was to construct a constant voltage VREF that has small

variation with temperature and supply voltage, moreover to minimize

the noise of this voltage reference.

Two Stage Differential Op-amp:

Aug, 09 - Dec, 09

. Built a high gain differential amplifier using Cadence and other

simulation models. This required basic knowledge about the

working of transistor in saturation region and proper voltage swing.

DDR2 Controller Design Project:

Aug, 09 - Dec, 09

. Designed and implemented a 512Mb (32 X 16 4 banks) DDR2 controller in

Verilog HDL and simulated the designs along with Denali's DDR2 model

using Cadence NC-Verilog.

Directed Research - IC classification using Digital Testing Techniques:

Aug, 09 - May, 10

. Worked on IC classification project using ATPG tools and tested them

with respect to their error rate and significance. This work can help

a company increase the yield and reduce the cost of terminating

unwanted IC's.

16 bit Motion Estimator for a DSP:

Jan, 09 - May, 09

. Designed and implemented a 16 bit Motion Extimator(M.E.) kernel for a

DSP on cadence using nanosim which was used to calculate the absolute

diference between the correponding pair of pixels in two blocks.

2.048Kbit SRAM Design:

Jan, 09 - May, 09

. Designed and implemented a 2.048Kbit SRAM with 16 bit wide words and a

complete read write operation . The design was made in such a way so

as to make the design robust, fast and efficient using cadence and

nanosim tools.

24 Bit ADDER

Jan, 09 - May, 09

. Designed and implemented a 24 bit adder using a Ladner - Ficher

architecture on cadence, optimized it and tried to find an equal rise

and fall time delay using Nanosim.

Computer System Organization

Aug, 08 - Dec, 08

. Implemented 5 staged pipeline using ePD (Electronic Product Design)

tool at Gate level design, and also executed the MIPS assembly code.

. Designed and implemented 32-bit adder, ALU unit, single cycle CPU and

multi cycle CPU using ePD.

MOS VLSI Circuit Design

Aug, 08 - Dec, 08

. Designed and implemented a working Neuron using Cadence.

. Designed and optimized a D flip-flop using the basic building block on

Cadence, tried to get equal rise and fall time and simulated it using

Hspice.

Semiautomatic Electric Wheel Chair

Jan, 08 - May, 08

. Developed a wheel chair which can get converted into a stretcher. The

project required thorough concepts about Mechanical, Electronic and

Electrical engineering.

HONORS:

. Viterbi Graduate Students Association (VGSA) Senator for Electrical

Engineering Jan, 09 - May, 10

. Awarded an assistantship of INR 25000.00 from Gujarat Council of

Science and Technology, Government of Gujarat, in recognition for our

final year project.

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