Engineer Electrical Engineering
Resume:
Raviteja Gollamudi
Piscataway, NJ 08854
*******@*****.***
OBJECTIVE To obtain a full time position in the fields of telecommunications,
digital signal processing, and electrical engineering.
EDUCATION M.S., Computer and Electrical Engineering, Fall 2010 (expected)
Rutgers, the State University of New Jersey, New Brunswick, GPA
3.5/4.0
B.S., Computer and Electrical Engineering, May 2007
Rutgers, the State University of New Jersey, New Brunswick, GPA
3.4/4.0
ENGINEERING Development and Modeling Circuit Simulation Programming/Scripting
SKILLS Tools and Layout Tools Languages
MATLAB/SIMULINK OrCAD circuit C, C++
CoWare SPD simulation tools TCL scripting for
CodeWarrior ExpressPCB test automation
Code Composer Studio
Eclipse
Visual Studio
Test and Measurement Development Platforms Documentation and
Equipment Office tools
RF oscilloscopes, Windows XP/Vista/7 Doxygen for source
spectrum analyzers and Linux Red Hat/ Ubuntu code documentation
signal generators Microsoft Word,
High-speed logic Excel, PowerPoint,
analyzers OneNote, Visio
Agilent 89600 VSA
software
Agilent Signal Studio
software
Keithley Signalmeister
software
WORK EXPERIENCE 1xEVDO Femtocell Development (Global Wireless Technologies) (Jan
2009 - present)
Lead DSP Engineer
Worked in a team environment to design and develop an EVDO Layer one
solution.
Designed and implemented efficient forward link bit level processing
algorithms such as, CRC generation, turbo encoding, data scrambling,
channel interleaving for fixed point DSP processors.
Designed and implemented efficient forward link spreading algorithms
to perform Walsh and complex PN spreading operations for fixed point
DSP processors.
Designed and implemented efficient reverse link algorithms to
perform complex PN generation and de-spreading, and acquisition
operations for fixed point DSP processors.
Designed and implemented efficient reverse link algorithms to
perform RRI, DRC, ACK and DSC channel de-spreading and decoding
operations for fixed point DSP processors.
Designed and implemented efficient reverse link algorithms to
perform data channel de-spreading, demodulation, hybrid-ARQ
combining and channel de-interleaving and de-scrambling operations
for fixed point DSP processors.
Designed and implemented RTOS based multi-core task scheduling
framework to implement the Layer one application.
Designed and implemented processing threads consisting of layer
multiple one modules to be executed by the scheduling framework.
Defined test cases for module, channel and system level tests based
on C.S0032-A v2.0 Minimum Performance Standards document. Tests were
performed to measure functional and performance metrics.
Managed development of TCL scripts implementation to perform Layer 1
testing.
Complete knowledge of the C.S0024-A v3.0 cdma2000 High Rate Packet
Data Air Interface Specification. Partial knowledge of the C.S0002
Physical Layer Standard for cdma2000 Spread Spectrum Systems
specification.
3GPP LTE Femtocell Development(Global Wireless Technologies) (May
2009 - present)
DSP Engineer
Developed downlink LTE modules given in the TS 25.211, TS 25.212 and
TS 25.213 specifications.
Designed and implemented bit level processing for PBCH, PCFICH,
PHICH and PDCCH control channels
Designed and implemented efficient downlink modules such as CRC-16,
convolutional encoder, turbo encoder, rate matcher, scrambler and
modulator.
Designed and implemented resource mapping modules for downlink PBCH,
PCFICH, PDCCH, PHICH, PDSCH, Reference signals and Synchronization
signals.
Designed and implemented RTOS based multi-core task scheduling
framework to implement the Layer one application.
Designed and implemented processing threads consisting of layer
multiple one modules to be executed by scheduling framework.
Performed integration testing and verification of downlink control
channels from bit level processing to IFFT samples output.
Verified proper functionality of downlink control channels operation
using keithley Signalmeister VSA software.
RESEARCH WORK Performed a study of implementing the Wimax physical layer using
wavelet packet modulation. The IFFT/FFT transmit and receive modules
were replaced using the inverse wavelet packet transform and wavelet
packet transform and the following was observed
BER performance in AWGN, slow rician fading and fast rayleigh fading
channels.
BER performance in AWGN channels for different scales of wavelet
packet reconstruction and decomposition
BER performance in fading channels for higher wavelet scales
BER performance for different channel conditions based on used
wavelet.
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