Project Signal Processing

Indukuri Teja V S N Varma

University of California, Santa Barbara, Department of ECE

**** **** ****** *** #**, Sunnyvale CA-94086

E-mail: ************@*****.***

Phone: 805-***-****

OBJECTIVE

To obtain a fulltime/internship position in a challenging environment

to build my career in the field of Computer Engineering and to utilize my

ability to prove myself as design engineer.

EDUCATION

University of California, Santa Barbara

. Master of Science (Sep-2007-June-

2010)

. Major: Computer Architecture and Signal Processing

Andhra University

. Bachelors in Engineering (Aug 2003-May 2007)

. Major: Electronics and Communications Engineering

TOOLS AND TECHNOLOGIES

. Simulation and Modeling tools : MATLAB, MAX, SUE, Spice.

. Hardware Description Languages: Verilog, VHDL, System Verilog.

. Software Languages : C, C++, Java,

Assembly language 8085.

. Operating systems : Windows, Linux and Mac OS.

. Data Base Administrative tools : MySQL, Oracle

PROJECTS DONE AND KEY POINTS

I. Super scalar instruction dispatch unit using Tomasulo's algorithm:

. Tomasulo based dual instruction dispatch unit with two-phased

clocking.

. Control of the structural and data dependent hazards.

. Reservation stations to control the flow of instructions until the

arithmetic units are ready.

. Buses are independent and contain lines for data and the tags.

. Register file for snooping the data from the buses and the events of

the four registers.

. Individual and global test benches for each modules using Verilog.

II.

Two level cache design with set associative cache and snooping mechanism:

. Cache architecture consisting of a four-way set associative cache with

two levels of caching system with two phased clocking.

. The design is implemented for four sets of cache with a shared memory.

. The project provides snooping techniques for cache book keeping and

split cycle memory management.

. Individual test benches have been created for each module as well for

the entire project.

III. ASIC projects using Verilog:

. Implementation of state machine.

. Processor along with memory unit.

. Decoders, flip-flops, multiplexers and seven segment displays.

IV. Image forensic in detecting forgeries in scientific images using

MATLAB:

. Image segmentation technique using normalized cut.

. Detection of intensity change, duplication and change in structure.

. Tried to implement automatic detection.

V. Security in data communications with RSA Algorithm using MATLAB:

. Implementation of RSA algorithm for cryptography with DES.

. Asymmetric key cryptographic technique.

. Generation of public key and a private key.

. MATLAB was used for the implementation.

COURSEWORK

Computer Architecture : Advanced Computer Architecture: Super Computers,

Advanced Computer Architecture: Distributed Systems,

Digital Design with VHDL and synthesis and Fault Tolerant Computing.

Signal Processing:

Digital Signal Processing, Digital Image Processing, Fourier analysis and

Information Theory.

RELATED SKILLS

. Self-

starter, flair for hard work, challenges and ability to work under little gu

idance.

. Excellent communication skills. Able listener and good team player.

WORK EXPERIENCES:

. Summer interned at Vector institute and technologies for a final year

project at Hyderabad April -August 2006.

1. Designed and implemented RSA algorithm based on cryptography

techniques using MATLAB.

2. Been the project leader.

. Worked in the digitization library in UCSB libraries in Summer 2009.

. Been a TA for Mathematics in Andhra University " Matrices and Algebra"

. 2005

REFERENCES

Available on request

Contact this candidate