Design Project
Resume:
VIJAY BAHADUR
*********.**@*****.***
+91-903*******(Mobile)
Career Objective
Seeking assignments in System Design Engineering (VLSI) with an organization of repute.
Synopsis
Presently working in CDAC Bangalore
More than 2 and half years of experience in the field of VLSI on various projects.
Very good knowledge of ASIC/FPGA design flow.
Very good Knowledge of Advanced Digital design concepts.
Implemented Dictionary attack for different password search engines.
An efficient and effective RTL design and verification using VHDL and Verilog.
Synthesized the design and verified the design on FPGA platform (Xilinx).
Design and development of Crypt IP cores on FPGA (Xilinx).
Expanded technical proficiency by undertaking various projects and attending seminars.
An excellent communicator with good analysing and problem solving skills.
Technical Skills
Languages : VHDL, VERILOG, System Verilog (Basics), C, C++, Linux shell scripting.
Tools : Cadence RTL compiler, Questa sim, Xilinx ISE, Vivado, Chipscope - PRO, Emacs,
Vim etc.
: CPU & Memory Architecture, PCI –Express, USB, OTN etc.
System Architecture
Operating systems : Linux, Windows XP, Windows 7.
Educational Qualification
2012 Post- Graduate Diploma in VLSI from Centre for Development of Advanced Computing
(CDAC), PUNE.
Percentage 75.87
2011 B. Tech (Electronics and Communication) G.B.T.U, Lucknow
Percentage 74.34
2006 HSE(+2) Uttar Pradesh Board
Percentage 81.80
2002 SSLC (10th) Uttar Pradesh Board
Percentage 59.00
Organisation Experience
Employer Position Experience Domain
Project Engineer-I RTL design &
CDAC, Bangalore 08 Oct 2012 to till date
verification
Projects Undertaken
Title : Design and development of Side Channel Attack resistant True Random Number
Generator on RCS (Reconfigurable Computing Systems) Low Profile Card.
Role : RTL Design, Verification, Synthesis, Implementation, Testing, API interface,
Documentation
HDL : Verilog, VHDL
Tools : Xilinx ISE14.2, Questa sim.
Scope : The project was carried out to develop a side channel attack resistant True Random Number
Generator on RCS card.
Challenges : Protecting True Random Numbers form various Side Channel Attacks.
Title : Design and development of Pipelined Triple DES and IDEA decryption engine IP Core
on RCS (Reconfigurable Computing Systems) Low Profile Card.
Role : RTL Design, Verification, Synthesis, Implementation, Testing, API interface,
Documentation
HDL : Verilog, VHDL
Tools : Xilinx ISE14.2, Questa sim.
Scope : The project was carried out to develop a pipelined Triple DES and IDEA decryption engine
IP Core on RCS card.
Challenges : Design of Pipelined IP core running at 300 MHZ on Virtex-5 FPGA.
Title : Design and development of DES (Data encryption Standard) cipher text only attack
and DES Brute –force key search on RCS Low Profile Card, DINI D2076K10 board and
PICO M503 board.
Role : RTL Design, Verification, Synthesis, Implementation, Testing, API interface,
Documentation
HDL : Verilog, VHDL
Tools : Xilinx ISE14.2, Questa sim.
Scope : The project was carried out to find the 56-bit key of DES using cipher text only attack and
Brute-force attack. This design was implemented on three different FPGA boards
(Reconfigurable Computing Systems (RCS) Low Profile Card, DINI DN2076K10, and PICO
M503).
Challenges : Cracking 56-bit DES key within one day time.
Title : Design and development of AES (Advanced encryption Standard) cipher text only
attack key search on RCS Low Profile Card, DINI D2076K10 board and PICO M503
board.
Role : RTL Design, Verification, Synthesis, Implementation, Testing, API interface,
Documentation
HDL : Verilog, VHDL
Tools : Xilinx ISE14.2, Questa sim.
Scope : The project was carried out to find the 128-bit key of AES using cipher text only attack.
This design was implemented on three different FPGA boards (Reconfigurable Computing
Systems (RCS) Low Profile Card, DINI DN2076K10, and PICO M503).
Challenges : Cracking AES key with max possible key search rate not achieved till now.
Title : Design and development of PDF R2, R3, R4, R5 Password search on RCS
(Reconfigurable Computing Systems) Low Profile Card, DINI DN2076K10 board, and
PICO M503 board.
Role : RTL Design, Verification, Synthesis, Implementation, Testing, API interface,
Documentation
HDL : Verilog, VHDL
Tools : Xilinx ISE14.2, Questa sim.
Scope : The project was carried out to develop a dictionary based password search engine of PDF
R2, R3, R4, R5 for password length 5 to 20 on three different boards (RCS card, DINI
DN2076K10 board and PICO M503 board). PDF uses cryptographic algorithm for encryption
and decryption.
Challenges : Achieving search rate of millions of passwords per second.
Title : Design and development of MS office-2003 Crypto-API Password search on RCS
(Reconfigurable Computing Systems) Low Profile Card, DINI DN2076K10 board, and
PICO M503 board.
Role : RTL Design, Verification, Synthesis, Implementation, Testing, API interface,
Documentation
HDL : Verilog, VHDL
Tools : Xilinx ISE14.2, Questa sim.
Scope : The project was carried out to develop a dictionary based password search engine of MS
office-2003 for key length 5 to 16 & password length 5 to 19 on three different boards (RCS
card, DINI DN2076K10 board and PICO M503 board). MS office-2003 uses cryptographic
algorithm for encryption and decryption.
Challenges : Achieving search rate of millions of passwords per second.
Title : Design and development of MS office-2007 Password search on RCS (Reconfigurable
Computing Systems) Low Profile Card, DINI DN2076K10 board, and PICO M503
board.
Role : RTL Design, Verification, Synthesis, Implementation, Testing, API interface,
Documentation
HDL : Verilog, VHDL
Tools : Xilinx ISE14.2, Questa sim.
Scope : The project was carried out to develop a dictionary based password search engine of MS
office-2007 for password length 5 to 19 on three different boards (RCS card, DINI
DN2076K10 board and PICO M503 board). MS office-2007 uses cryptographic algorithm for
encryption and decryption.
Challenges : Achieving search rate of thousands of passwords per second.
Title : Design and development of Winrar unencrypted header & Winrar encrypted header
Password search on RCS (Reconfigurable Computing Systems) Low Profile Card, DINI
DN2076K10 board, and PICO M503 board.
Role : RTL Design, Verification, Synthesis, Implementation, Testing, API interface,
Documentation
HDL : Verilog, VHDL
Tools : Xilinx ISE14.2, Questa sim.
Scope : The project was carried out to develop a dictionary based password search engine for
Winrar Encrypted Header design and to accelerate AES key and AES initial vector generation
for Winrar unencrypted design for password length 5 to 13 on three different boards (RCS
card, DINI DN2076K10 board and PICO M503 board). Winrar uses cryptographic algorithm
for encryption and decryption.
Challenges : Achieving search rate of thousands of passwords per second.
Academic Project
Title : Design and verification of UART
Role : RTL Design, Verification, Documentation (Done at C-DAC, PUNE)
HDL : Verilog, VHDL
Tools : Xilinx ISE14.2, Questa sim.
Scope : The Universal Asynchronous Receiver Transmitter (UART) is a popular and widely-used
device for data communication. It has FIFOs for the receiver/transmitter data buffering and
shift register for parallel to serial conversion and vice-versa. Our reference design has a DMA
interface with baud rate of 57600 bps 16 bytes deep Asynchronous FIFOs and 8 bits of data in
a frame with 1 start bit, parity bit and 1 stop bit.
Trainings, Conferences & Seminars
Attended 5 days training on Bluespec language.
Attended National Workshop on SIDE CHANNEL ANALYSIS sponsored by The National Board
for Higher Mathematics (NBHM).
Attended the workshop on “Future Trends in RF and Microwave Technologies” technically sponsored
by IEEE MTT-Society, SB Chapter IIT, Delhi as a member of organizing committee.
Attended IEEE PARA-COMPTECH 2013.
Personal Details
Name : Vijay Bahadur
Fathers Name : Mr. Raj Kumar
Date of Birth : 19-may-1990
Religion : Hindu
Present Address : House No.-35, Ground floor,
C/o Ganesh Rao 8th cross M.T Street,
Vasanth Nagar, Bangalore-560052
Permanent Address : Vill- Matheri, Post- Chandseena
Distt- Muzaffarnagar, Uttar Pradesh - 251201
E-mail Id : *********.**@*****.***
Phone : 090********
References
Reference 1: SAURAV KUMAR ANAND
Technical Lead,
HCL, Noida
U.P, India
****************@*****.***
Reference 2: ANESSH R
Technical officer,
UCHR Group,
CDAC Bangalore
Karnataka, India
***********@****.**
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