Engineer Design
Resume:
Marcel Ching
***** ***** **** **. - ******, TX.
77379
*********@*****.***
Resume Of Qualifications
Senior Design Engineer with extensive experience in circuit and firmware
design, consistently delivered project on time for company-wide production.
Presented and maintained project plans and developments to team members,
achieved overall project cost savings and reduced NRE by meeting major
project milestones.
Served as consultant to engineering team during system design phase, lab
hardware debug, firmware development, device components and equipment
purchases.
Technical Skills
PowerView, Orcad schematic capture
Allegro, SpectaQuest board layout
Lattice ispLever/Orcad Quartus II CPLD, PAL, FPGA
Microchip MPLAB IDE, Keil Cx51 Development Tool (80C51, AT89C52)
Verilog-XL, SignalScan, Quad simulation
Tektronix logic analyzer TLA7000/Scopes DSA70000/TDR TDA8200
Iconnect/MeasureXtractor
UNIX, Windows, C, C++, Basic, Pascal, X86 MASM6.1
MS Office Suite (Words, Excel, Power Point, Project, Outlook)
Source File Management and Revision Control (RCS/VCS)
Professional Experience
Procurement Central Group Houston, TX.
Hardware/Firmware Design Engineer (05/2009 - Present)
Project Consultant for PCB and high speed electronic design and
development, schematic capture using Orcad, gerber data 274D/X, Fabrication
and assembly drawings, DFX.
Embedded Design and firmware development for ARM and 8051 microcontroller
devices. Methodologies: RTOS, embedded LINUX, Green Hills Integrity.
Planning and Management, replacement for end of life components. Inventory
planning and management based on production forecast, components evaluation
and purchasing.
Foxconn EMS Houston, TX.
Electrical Hardware Design Engineer (04/2004 - 12/2008)
Project lead for system CPLD/FPGA design and development (Lattice MachXO
1200, 2280, Altera MAXII Family). Implemented high level port list mapping
and bank partitioning for 1.8, 2.5, 3.3V and device I/O port connection
based on system and components interface requirements, developed low level
drivers, sub-modules tasks for complete functional coverage, developed
simulation environment and test stimulus for code debug ahead of prototype
hardware. Firmware functions included user interface (power button on/off,
power supply, fan, riser and option card removal), system safety power
up/down control for VRM modules and on board DC/DC controllers, general
scan chains for inter-chip (I2C) input/output communication protocol for
remote front panel and chipset, enclosure and components high temperature
monitoring via EMC1001,1002 1043, 1053, system alert and
operational self-degradation visual warning via LED, boards
and fans monitoring via front panel LCD, load balancing, interlock
chain for processors,
Marcel Ching
Page Two
Professional Experience (continued)
internal plug-in cards and chassis panels, system status and diagnostics.
Organized demonstration on system capabilities in detection and recognition
upon system faults, high temperature warning for components and subsystem
enclosure. Scheduled meeting on regular basis for code and firmware
specification review, developed system verification and qualification for
engineering platform. Provided complete acceptance test generation checkout
and developed built-in firmware test with external pads for lab
troubleshooting and during initial factory production runs.
Primary involvement 2P server systems (Intel/AMD processor, DDR3/DDR2, PCI,
PCI-E, I2C, USB, RS232, SAS, SATA), area of responsibility Signal Integrity
Verification, power supply and DC/DC controller design proposal, board
circuit and high
speed signal backplane developments, system power budget, BOM, test plan
qualifications. Kept engineering team in constant focus throughout project
with regular
update on new system operations and organized weekly technical meeting.
Created and developed different templates and software tools to manage and
streamline
code development, cut review and submission process time in half by
eliminating
overlaps and redundancies, which allowed the team to meet schedule and
successfully
reduce time to market by 30%.
Other area of responsibility included technical guidance and design
recommendation across all X86 platforms.
Hewlett-Packard (Formerly Compaq) Houston, TX.
Design Engineer (09/2002 - 11/2003)
Responsible for product test strategy and planning, design of custom test
hardware and ATE fixtures for worldwide board production. Extended
technical knowledge to team in area of Hot Plug interface, PCI-X, PCI-E.
Designed and co-developed custom DDR memory testers, including firmware to
enable/disable power rails, initializing the DIMM module and performed low
level test (read/write to all locations).
Designed and developed portable battery powered LED display testers for
hardware functional verification.
Other duties included board level functional debug during initial
prototype, pilot build and product ramp up, high speed PCB design, board
layout, CPLD and FPGA code development.
Hardware Design Engineer (07/1996 - 09/2002)
Performed system and board level design for 8-way Intel architecture, board
debug, and system functional verification.
Designed and developed first industry Hot Plug RAID Memory interface board
for server systems including firmware development for power rail monitoring
(2.5, 3.3, 5V) memory card insertion and removal, initialization pass/fail
and module online and ready.
Designed and developed 4P CPU host board for Intel Xeon processors and Hot
Spare boot pal for multiprocessor host systems, primary function to allow
safe system boot when one or more processor has failed the built-in test.
Developed technical reports, organized presentations and demonstrations of
detail functional operations at system and subsystem level as well as
interface protocol between chipsets. Duties also included board and system
level simulation, schematic capture,
board layout, in-depth test, hardware debug and timing analysis.
Marcel Ching
Page Three
Professional Experience (continued)
System Simulation Engineer (05/1989 - 07/1996)
Board, system level simulation and development of complex model for company-
wide distribution, provided verification strategy and test support for all
HP custom ASIC chipsets, PCI Compliance, functional and gate level
simulations. Test vector and stimulus generation for custom Asics model
development, testing and code verification.
Designed and developed system and board level simulation for desktops and
servers, bus functional model for Intel processors (80386, 80486, P6), bus
functional model for Intel
cache architecture (82496, 82491) and bus functional model for PCI bus
masters.
Duties included board level functional verification for ASIC chipsets,
memory and PCI devices.
System Compatibility Engineer (08/1988 - 05/1989)
Developed custom tools hardware/software for design and verification.
Characterized and verified EISA bus protocol and timing during initial
market introduction.
Developed Advanced Timing Verification Tool using HP logic analyzer trace
capture and system and peripheral test strategies as de-facto for EISA
system compatibility verification.
Control Data Corporation Bloomington, MN.
Aerospace/Government Division
Software Engineer (10/1985 -
08/1988)
Maintained IBM disk drive firmware and developed custom tester OS Drivers.
Designed and developed boot EEPROM (CMP86, MS ASM) and BIOS for Multi Host
Test Station for high density militarized disk drives and acceptance test
and firmware for 8051 microcontroller. Low level code written in assembly,
test program developed using C and resultant hex code downloaded via ISP
cable.
Other duties also included coding, test and system debug using X86 CPU
emulators.
Educations
MSCS DePaul University Chicago, Illinois.
BSEET Devry University Chicago, Illinois.
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