Engineer Design
Resume:
Adam Stark
Allen TX *****
Cell: 972-***-****
*.*****@**.**.***
http://hotjobs.yahoo.com/resumes/astark9930/maskdesiner1
EDUCATION
State University of New York at Farmingdale, Farmingdale, NY
Bachelor of Technology - Electrical Engineering, May 1995
GPA 3.15/4.0
SKILLS:
Cadence Virtuoso, Cadence VXL, Cadence Diva, Cadence Dracula
Cadence Assura for LVS/DRC/Parasitic Extraction
Cadence VCR, Cadence P-Cell Creation, Cadence Multiple Part Path
Mentor Calibre LVS/DRC/Parasitic Extraction/Metal Poly Fill
Synopsis Hercules DRC/LVS
PROCESSES:
X-FAB 0.6 Micron Modular Trench Isolated SOI CMOS
High Voltage Process
IBM 90nm IBM 130nm IBM 180nm
TSMC 65nm RF TSMC 90nm RF TSMC 130nm TSMC 350nm
DongBu 350nm
ST Microelectronics 130nm
Samsung 90nm
Texas Instruments Internal CO .26um RF Process
Texas Instruments Internal CO .35um RF Process
Texas Instruments Internal EO .35um Process
Texas Instruments Internal LBC4 LBC5 95V LBC7 95V Process (Power
Applications)
WORK EXPERIENCE:
QUALCOMM Inc, San Diego, CA August 2010 - Present
SENIOR ANALOG RF LAYOUT DESIGN ENGINEER (Contract)
TSMC 65nm RF process
*Perform analog mixed-signal IC Physical Design engineering functions and
responsibilities using CADENCE and MENOR CALIBRE software:
-create transistor level layouts from schematic (Cadence Virtuoso VXL)
-create block level layouts per schematic
-verify Physical Design database using Mentor Calibre DRC and LVS programs
-actively participate in resolving problems with LVS/DRC verification
-generate metal, poly and diffusion fill (symmetric if necessary for RF)
-run final DRC, LVS, ERC and Antenna checks
TEXAS INSTRUMENTS Inc, Dallas, TX December 2009 - June 2010
SENIOR ANALOG, RF LAYOUT DESIGNER (Contract)
Texas Instruments Internal EO .35um RF Process
Texas Instruments Internal CO .35um CMOS Process
Texas Instruments Internal LBC5 95V Process (Power Applications)
*Performed analog mixed-signal and RF IC Physical Design engineering
functions and
responsibilities using CADENCE software:
-created transistor level layouts from schematic (Cadence Virtuoso VXL)
-created block level layouts per schematic
-created, updated and verified Input/Output cells
-created and verified Padring
-created and verified Digitally Compensated Crystal Oscillator (DCXO)
-verified Physical Design database using company internally developed DRC
and LVS programs (K2)
-verified Physical Design database using Cadence Assura LVS Tool.
-used Cadence Virtuoso Chip Assembly Router (VCAR) to Place and Route
digital
blocks
TLSI Corporation, Melville NY July 2009 - October 2009
SENIOR ANALOG LAYOUT DESIGN ENGINEER (Contract)
X-FAB 0.6 Micron Modular Trench Isolated SOI CMOS
High Voltage Process
*Perform analog mixed-signal IC Physical Design engineering functions and
responsibilities using CADENCE software:
-created transistor level layouts from schematic (Cadence Virtuoso VXL)
-created block level layouts per schematic
-verified Physical Design database using Assura DRC and LVS programs
-performed parasitic extraction using Cadence Assura
-created and verified ESD structures
-created and verified Pad Ring
-use Cadence Multipart Path feature to efficiently generate guard rings and
shielded transmission
lines
-actively participated in resolving problems with LVS/DRC verification
-download and install additional layout functions from Cadence Source Link
web site: update
LSW, convert polygon to path, etc
-Top Level floor planing, routing, DRC/LVS verification, Antenna/ERC Check,
Tape - Out
procedure
MICROTUNE Inc, Plano, TX September 2008 - December 2008
SENIOR ANALOG RF LAYOUT DESIGN ENGINEER (Contract)
IBM 130 nm Process, IBM 180 nm Process
*Performed analog mixed-signal IC Physical Design engineering functions and
responsibilities using CADENCE software:
-created transistor level layouts from schematic (Cadence Virtuoso VXL)
-created block level layouts per schematic
-verified Physical Design database using Assura DRC and LVS programs
-actively participated in resolving problems with LVS/DRC verification
-performed parasitic extraction using Cadence Assura
QUALCOMM Inc, San Diego, CA April 2008 - September 2008
SENIOR ANALOG RF LAYOUT DESIGN ENGINEER (Contract)
TSMC 65nm RF process
*Performed analog mixed-signal IC Physical Design engineering functions and
responsibilities using CADENCE and MENOR CALIBRE software:
-created transistor level layouts from schematic (Cadence Virtuoso VXL)
-created block level layouts per schematic
-verified Physical Design database using Mentor Calibre DRC and LVS
programs
-actively participated in resolving problems with LVS/DRC verification
-generated metal, poly and diffusion fill (symmetric if necessary for RF)
-run final DRC, LVS, ERC and Antenna checks
ANALOG DEVICES Inc, Longmont, CO October 2007 - April 2008
SENIOR ANALOG RF LAYOUT DESIGN ENGINEER (Contract)
TSMC 350nm Process, DongBu 350nm process
*Performed analog mixed-signal IC Physical Design engineering functions and
responsibilities using CADENCE and SYNOPSIS Hercules software:
-created transistor level layouts from schematic (Cadence Virtuoso)
-created block level layouts per schematic
-verified Physical Design database using Hercules DRC and LVS programs
-verified Physical Design database using Assura DRC and LVS programs
-created and verified ESD structures
-created and verified Pad Ring
-used Cadence Multi Part Path feature to efficiently generate guard rings
and shielded transmission
lines
-actively participated in resolving problems with LVS/DRC verification
-created new parametrized cells (P-Cells)
-downloaded and installed additional layout functions from Cadence Source
Link web site: update
LSW, convert polygon to path, etc
TYCO ELECTRONICS, Morristown, NJ March 2007 - October 2007
SENIOR ANALOG RF LAYOUT DESIGN ENGINEER (Contract)
IBM 130nm Process, IBM 180nm Process, ST Microelectronics 130nm Process
*Performed analog mixed-signal and RF IC Physical Design engineering
functions and responsibilities
using CADENCE and Mentor Graphics software:
-created transistor level layouts from schematic (Cadence Virtuoso)
-created block level layouts of major blocks: MIXER, LNA, VCO etc.
-verified physical design database using Mentor Calibre LVS/DRC Tools
-performed parasitic extraction using Mentor Calibre
-created new parametrized cells (P-Cells)
-used Cadence Multi Part Path feature to efficiently generate guard rings
and shielded transmission
lines
-downloaded and installed additional layout functions from Cadence Source
Link web site:
update LSW, convert polygon to path, etc
-actively participated in resolving problems with LVS/DRC verification
-run final DRC, LVS, ERC and Antenna checks
ALEREON INC, Austin, TX November 2006 - March 2007
SENIOR ANALOG RF LAYOUT DESIGN ENGINEER (Contract)
TSMC 130nm Process, IBM 90nm Process, Samsung 90nm Process
*Performed analog mixed-signal and RF IC Physical Design engineering
functions and responsibilities
using CADENCE and Mentor Graphics software:
-created transistor level layouts from schematic (Cadence Virtuoso)
-created block level layouts of major blocks: MIXER, LNA, VCO etc.
-verified physical design database using Mentor Calibre LVS/DRC Tools
-performed parasitic extraction using Mentor Calibre
-created new parametrized cells (P-Cells)
-used Cadence Multi Part Path feature to efficiently generate guard rings
and shielded transmission
lines
-downloaded and installed additional layout functions from Cadence Source
Link web site:
update LSW, convert polygon to path, etc
-actively participated in resolving problems with LVS/DRC verification
-run final DRC, LVS, ERC and Antenna checks
WIQUEST COMMUNICATIONS, Allen, TX March 2006 - November 2006
SENIOR ANALOG RF LAYOUT DESIGN ENGINEER
TSMC 90nm RF Process
*Performed analog mixed-signal and RF IC Physical Design engineering
functions and
responsibilities using CADENCE and Mentor Graphics software:
-created transistor level layouts from schematic (Cadence Virtuoso)
-created block level layouts of major blocks: MIXER, LNA, DCXO, TXFE, VCO
etc.
-verified physical design database using Mentor Calibre LVS/DRC Tools
-performed parasitic extraction using Mentor Calibre
-created new parametrized cells (P-Cells)
-used Cadence Multi Part Path feature to efficiently generate guard rings
and shielded transmission
lines
-downloaded and installed additional layout functions from Cadence Source
Link web site:
update LSW, convert polygon to path, etc
-actively participated in resolving problems with LVS/DRC verification
parasitic extraction and
simulation
-generated metal, poly and diffusion fill at the full chip level
-run final DRC, LVS, ERC and Antenna checks
-responsible for Tape-Out procedure and submission of GDS file to TSMC
SIRIFIC WIRELESS Inc, Richardson, TX January 2005 - March 2006
SENIOR ANALOG, RF LAYOUT DESIGN ENGINEER
TSMC 130nm Process
*Performed analog mixed-signal and RF IC Physical Design engineering
functions and
responsibilities using CADENCE and Mentor Graphics software:
-created transistor level layouts from schematic (Cadence Virtuoso)
-created block level layouts of major RF blocks:RX/TX, VCO, LNA, DCXO
-verified Physical Design database using Mentor Calibre and Cadence Assura
LVS/DRC Tools
-utilized auto routing tool - Cadence VCR/VCAR to speed up creation of
small and medium size
digital blocks
-performed parasitic extraction (Mentor Calibre)
-created new parametrized cells (P-Cells)
-used Cadence Multi Part Path feature to efficiently generate guard rings
and shielded transmission
lines
-downloaded and installed additional layout functions from Cadence Source
Link web site: update
LSW,convert polygon to path, etc
TEXAS INSTRUMENTS Inc, Dallas, TX November 2000 - January 2005
SENIOR ANALOG, RF LAYOUT DESIGNER
Texas Instruments Internal CO .26um RF Process
Texas Instruments Internal CO .35um RF Process
Texas Instruments Internal LBC4 LBC5 60V Process (Power Applications)
*Performed analog mixed-signal and RF IC Physical Design engineering
functions and
responsibilities using CADENCE software:
-created transistor level layouts from schematic (Cadence Virtuoso)
-created block level layouts per schematic
-created block level layouts of major RF blocks:RX/TX, VCO, LNA, DCXO
-verified Physical Design database using company internally developed DRC
and LVS programs
-verified Physical Design database using Mentor Calibre and Cadence Assura
LVS, DRC Tools
-performed parasitic extraction (Cadence Diva)
-utilized auto place & route tools (Cadence VCR, Silicon Ensamble)
TEXAS INSTRUMENTS Inc, Richardson, TX March 1998 - November 2000
MICRON TECHNOLOGY LLC Richardson, TX
PHYSICAL LAYOUT DESIGNER
*Performed IC Physical Design engineering functions and responsibilities
using CADENCE
software:
-created transistor level layouts from schematic (Cadence Virtuoso)
-created block level layouts per schematic
-verified Physical Design database using Diva DRC, Hercules Hierarchical
DRC and diva LVS,
Hercules Hierarchical LVS programs
-utilized auto place & route tools (IC Craftsman)
-ensured that critical signal routing met IC Design Engineer's
requirements.
-work very closely with the IC Design Engineer to ensure a complete, error
free layout package.
LUCENT TECHNOLOGIES, Allentown, PA October 1995 - March 1998
PHYSICAL LAYOUT DESIGNER
*Performed IC Physical Design engineering functions and responsibilities
using Lucent internal CAD
software:
-created transistor level layouts from schematic
-created block level layouts per schematic
-routing of critical signals and power buses
-fine routing and compaction
-parasitic extraction
-verified Physical Design database using DRC and LVS programs
-provided Physical Design database and associated information for mask
generation
-ensured that critical signal routing met IC Design Engineer's
requirements.
-worked very closely with the IC Design Engineer to ensure a complete error
free layout package.
-finalized the device layout, block placement and routing to ensure the
Physical Design meets
manufacturing design rules and the IC Design Engineer's performance
requirements.
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