Design Engineer

Joseph C. Rhodes, III

***** ***** ****** **. **** 36 Cell: 512-***-****

Austin, TX 78747 **********@*******.***

SUMMARY

Proven strong contributor with 10 years of direct experience in the

semiconductor industry (7 years in VLSI implementation and 3 years in

system and product engineering). Implemented physical designs meeting

timing, power, area and other physical goals for both 2+ GHz x86 CPU cores

(in 65nm and 45nm) and x86 chipsets (in 130nm and 90nm) utilizing both full

custom (manual design) and automated design flow. Understand VLSI CAD

tools and wrote additional scripts, when needed, in order to manage files

in the design database as well as to automate several design specific

tasks. Supported products for the embedded market segment through board

design, system bring up, and benchmarking of custom boards that proved

functionality and optimized CPU performance and customer support.

SKILLS / CORE COMPENTENCIES

Operating environments Unix/LINUX, Windows XP/Office

Programming languages PERL, TCL, C, protected mode x86 assembly

Formal verification Cadence LEC (standard EC, clock domain CDC, low power

CLP, ECO)

Implement design from Either by hand (Verilog or Mentor da), or using tools

Verilog specification (Synopsys dc_shell, Cadence rc, First Encounter), PTSI

timing closure

Interpret and address Timing/noise reports from Primetime or ETS and

qor metrics physical checks form Astro or Calibre, perform ECO to

meet DFM or functional requirements

Documentation Word, PowerPoint, Twiki, Framemaker

Collaboration Livemeeting, provided and coordinated training, setup

TWIKI and forms

Content management MySQL, Designsync (Source control management SCM)

PC architecture X86 ops, system buses (ISA, PCI, and AGP)

System design and use PCB design / FPGA (Xilinix or Lattice)

for bring up /

optimization

EMPLOYMENT

04/08-04/09 Freescale, Austin, CAD Software Engineer

TX

Part of small centralized CAD organization that provided design support

in the form of common tool automation, documentation / collaboration, and

additional support enabling design groups across the entire company

. Worked with designers in various different groups to understand their

needs and methods to accomplish their project needs

. Met with tool vendors (mainly Cadence) to address tool requirements

vs. current capabilities and recommended best practices

. Developed automation scripts in Tool Control Language (TCL) to provide

a common methodology allowing various design teams to efficiently

utilize the design tools. This was managed as part of larger project

through using Design Sync as a SCM system.

. Co-developed new TCL wrapper for formal verification automation using

Cadence Conformal Logical Equivalence Checker (LEC) with one other

engineer in Israel

o Enabled smooth transition from the synthesis phase to formal

verification related phases

o Developed and documented automated ECO flow to make targeted

last minute changes taking advantage of formal verification

tools as opposed to the time-consuming manual process

o Added and documented several features to standard equivalency

checking flow

o Implemented rapid changes to automated procedure allowing for

more flexibility

o Provided several training sessions on the new features that were

created and setup several online collaborative environment for

the design community to make effective use of these new

capabilities

. Responded to Remedy tickets from different design teams requesting

support relating to formal verification (quality checks of the clock

synchronization in HDL, equivalency between HDL and physical netlist,

and ECOs)

06/01-04/08 AMD, Austin, TX Design Engineer

10/02-04/08 (CPU Design)

Hand implemented logic to meet timing, area, and power goals and verify

implementation to model for 2+ GHz x86 microprocessor

. 01/04-04/08 Optimized Floating Point Unit (FPU) for multicore K8 in

both 65nm and 45nm

o Partitioned the Floating Point Unit design into 17 smaller sub

pieces for our team to work with simultaneously

o Worked on 3 sub blocks (SLMs) to meet all timing area metrics

(Some new design, some optimization of existing design)

o Performed more detailed timing and electrical analysis of one

route level module (RLM) consisting of four routed SLMs combined

together and extended out to the rest of the chip to resolve all

issues (timing, electrical, physical, and tool related). Data

from RLM was used to make more accurate SLM designs and

architectural trade offs in subsequent iterations

o Translated several blocks to make use of the newer CAD

environment for the 45nm Shanghai project. Converted 20

schematics from Mentor da to Mentor IC Station, converted

placement of 6 blocks to new placement language

o Member of six person team that performed full chip false path

timing review before 65nm Barcelona tapeout

o Preformed cross module hand edits for timing, noise, and other

manufacturing issues

. 10/02-01/04 - Designed four issue x86 instruction decode from RTL

description (New core)

o Designed single cycle four issue instruction cracker (all

previous AMD processors were three issue or less) to a timing

goal of 450ps

o Designed 32 byte instruction skid buffer (selected up to four

instructions, depending on length, from buffer and stored off

any remaining bytes for next cycle processing)

o Synthesized and Auto Place and Route (APR) large decode table

(between 90K and 100K gates) providing a quick first pass

reasonable placeholder

06/01-10/02 (Chipset Design)

Provided chipset solutions to enable the AMD CPU platform

. Backend implementation of Hyper Transport to PCI / PCI-X bridge (over

700k gates) in an ASIC flow

o One of three authors and one of two maintainers for entire

backend compile script

o Ran biweekly full chip builds using backend scripts, reviewed

the quality of results (qor), made improvements to help close on

design goals (revised floorplan, changed tool optimizations,

updated timing budgets, and feedback of other required design

changes)

. Developed netlist parser written in PERL and preformed several

optimizations on the physical netlist (scan chain balancing and a

large number of last minute performance fixes)

. Reviewed all physical design checks before passing design on to

physical layout

. Supported effort to be first to market with an AGP 3.0 platform by

producing a test chip to mimic a graphics card (since there were no

AGP 3.0 cards available to bring up the platform)

o Developed PERL script to generate random AGP bus traffic test

patterns and validated 96%+ logical test coverage using Verisity

Surecov resulting in error free tape out of test chip that was

used to bring up first K8 platforms

ADDITIONAL EXPRIENCE

01/97-06/00 (every other AMD, Austin, TX Co-op

semester)

. Member of in-house design team that was quickly reconstituted to

enhance chipset features for the K7 system platform that were lacking

relative to the competition

o Wrote PERL script to migrate two processor K7 Northbridge

chipset to new cell library allowing leverage of old reference

design as a starting point

o Worked on synthesis and timing analysis / optimization on bus

synchronization unit

. Supported embedded customers that used established parts which were no

longer supported by a design team

o Solved a customer system level JTAG issue by running processor

simulations on Zycad (a software simulation environment) and

ultimately preformed an ECO to fix bugs in AMD Elan SC520 (486

system on a chip)

o Characterized running K6 processor at a lower voltage and single-

handedly implemented a system level test allowing the Embedded

Processor Division to verify K6 in system stability at that

lower voltage to delivered critical customer samples stable and

on time (received Vice President's Spotlight Award)

o Created interactive Web based tools using PERL Common Gateway

Interface (CGI) scripts that found recurring sleep mode problem

on 486 wafers at certain chip (die) locations improving yield

fallout substantially

. Provided real platforms to test processors and other enablement

technology to guarantee reliable and optimal real world performance

o Designed and debugged K6 processor compare printed circuit board

with several other engineers that debugged a bus cycle

discrepancy in some K6 processors

o Designed K7 processor voltage simulation board, using a Xilinx

4036 FPGA, for a fast reliable voltage level conversion for the

K7 processor, which used different voltage level, HSTL (1.5V),

from the standard TTL (3.0V) logic on most motherboards

o Verified that several OSes (Windows and Unix based) booted on a

simulated K5 processor

o Performed K6 Fast PC benchmarking, using Winbench 97, that

determined the optimal bus speed used in the definition of the

AMD Super 7 design (100 MHz Socket 7 bus)

05/96-07/96 Compaq, Houston, TX Summer Intern

. Supported marketing by providing stable custom configured prototypes

for large customers by configuring, stability testing, shipping

workstations, and rebuilding returned units after the preview

. Reworked system boards to replace a backward capacitor on one lot

(about 30 systems) rather than send the units back for rework saving

two weeks

EDUCATION AND TRAINING

1995-2001 Southern Methodist University, Dallas, TX, BS in Electrical

Engineering with a minor in Computer Engineering and Mathematics

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