Engineer Project

SHAISHAV PARIKH

*** ****** **

Austin, Texas - **737

Phone: (C) 979-***-****

Email: ******.********@*****.***

OBJECTIVE:

Seeking challenging position in DFT to apply/enhance my skills and

background.

WORK EXPERIENCE:

ADVANCED MICRO DEVICES INC. (Jun 2005 - Present)

Structural-Test Lead for NextGen Low Power Core (Mar 2010 - Present)

Scheduling and milestone definitions.

Define Structural-Test strategy and flow details.

Define and verify scan test features and structures.

Develop the flow environment with revision control.

P1500 verification.

Train new hire on the flow and tools.

DFT Engineer for Low Power Core (Jun 2007 - Feb 2010)

Develop low effort synthesis flow for DFT checks.

Develop scan insertion flow for Core IP.

Cell library and custom array modeling for ATPG tools.

1149.1 JTAG verification.

Isolation wrappers verification.

Logic BIST verification.

Scan compression verification.

Generate and verify structural patterns at core level.

Translate structural patterns to SOC level and deliver them to product

group.

Debug and diagnose ATE fails during silicon bringup.

Involved in project cycle from core spec definition phase to production.

Train new hires on the flow and tools.

DFT Engineer for Low Power SOC (Jul 2005 - May 2007)

Scan based testing of DDR, Hyper transport, Client NorthBridge.

Cell library and macro modeling for ATPG tools.

Generate and verify structural patterns at SOC level for multiple design

revisions.

Debug and diagnose ATE fails during silicon bringup for multiple design

revisions.

Involved in project cycle from early SOC design definition phase to

production.

. TEXAS ENGINEERING EXPERIMENT STATION (Sep 2004 - May 2005)

Research Assistant on "Testing tri-state and pass transistor circuit

structures" project funded by AMD.

Spice simulations of 65nm tri-state structures to help develop gate level

models for higher fault coverage.

. ADVANCED MICRO DEVICES INC. (Jan 2004 - Aug 2004)

Product Development Engineer on Athlon products.

Scan pattern verification on teradyne and sapphire testers.

Debugging of tester, package and pattern issues.

EDUCATION:

. TEXAS A&M UNIVERSITY Jan 03 - Aug 05

Master of Science: Computer Engineering G.P.A.

3.58

TOOLS:

Synthesis Design compiler, RTL compiler

STA Primetime

Scan insertion DFT advisor, DFT compiler

ATPG Fastscan, Testkompress, Encounter Test, Tetramax, DFT

Max

Diagnosis Yield Assist

Simulators VCS, Verilog-XL

Waveform Viewer Verdi

Scripting Perl, Tcl

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