Training Design

**** *.**** ***** **. . Chicago, IL ***** Phone 773-***-**** . E-mail

**********@***.**

Svetlina Pencheva

OBJECTIVE

Electronics engineering with opportunity to use skills and

experience in Verilog, VHDL, Cadence, OrCAD and PADS.

EXPERIENCE

Electronic technician, PLEXUS, Buffalo Grove, IL

11/2008 - 06/2009

- Test, troubleshoot and calibrate medical equipment.

Practical training in ECAD Laboratory of Technical university

of Sofia 2003-2005

-Analog and digital circuit design, simulation and PCB

layouts.

EDUCATION

Illinois Institute of Technology (IIT), Chicago, IL

2006 - up today

Certificate program- Advanced Electronics.

Technical University of Sofia, Sofia, Bulgaria

Master of Science degree -Microelectronics, 2005

Bachelor of Science degree - Electronics, 2002

SKILLS

CAD programs:

- Schematic capture tools and PCB layout (OrCAD, PADS,

CADENCE, Mentor Graphics);

- VHDL and Verilog programming;

Experience with Xilinx FPGA and their respective development

tools;

Windows, Microsoft Word, Microsoft Excel;

Programming Skills - C, Tcl/Tk, C++, Pascal;

TRAINING/PROJECTS

CAD Tool Design for Static Timing Analysis by using Tcl/Tk and

C programming

Design and Synthesis of an 8-Bit Pipelined CPU using Verilog

HDL. The project included the development of ALU, buffers,

multiplexers, latches etc. The layout was tested using IRSIM.

Design CMOS Sub-Bandgap Voltage reference with stable output

parameters at variation of temperature, power supply and

technology parameters using PSpice and CADENCE. Two

technologies are used: AMS 0.35? Si CMOS and AMS 0.8? SiGe

BiCMOS.

PCB Layout

Layout of Bandgap Voltage Reference of AMS 0.8 SiGe BiCMOS

technology

Practical PCB training in EPIQ Electronic Assembly - 12 weeks

Manual and automated assembly of electronic components on PCB.

Module assembly: attaching the circuit board to other part,

such as plastic housing

Work Status: U.S. Permanent Resident

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