Engineer Manager

Frank Wang

408-***-**** **********@*****.***

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Test Automation Engineer

Design tools & flows - Test Generation & Automation ? Project Management -

Quality Improvement ? Scrum Master

SKILL SUMMARY

. Creation of verification environments, including software simulator

development and test automation.

. Detailed test plans and schedule generation, and project monitoring.

. Proficiency in C, C++, Perl, UNIX Shell Scripting, Tcl/TK.

. Familiar with Agile Software Development Process.

. Balanced software & hardware experience

. Self motivated team worker/leader.

PROFESSIONAL EXPERIENCE

GENERAL ELECTRIC SHANGHAI, CHINA, 2009-2011

Manager, Software Design & Test

Led a software team in POS (Point Of Sale) system design & test in Windows

environment, shortened the development & test cycle by utilizing the Agile

Software Development Methodology & new improved process, and achieved great

customer satisfaction.

. Led team that delivered quality products at a shorter time to market.

. Process improved in code review, code coverage/unit test, test coverage

matrix, test automation, and build (release) automation to ensure on-time

product delivery.

. As a Scrum Master, hosted sprint planning meetings, daily scrum meeting,

generated daily status, and Burndown Chart for closely monitoring the

team progress.

MACRONIX MICROELECTRONICS, SUZHOU, CHINA, 2003-2007

Manager, Verification

Led a verification team in testing and helping on quality improvement (code

review, test coverage etc.) for the following products: Cardbus/PCI

Adaptor, H.264 Baseline Decoder IP, and a multi-million gate LCD

Controller (Video Image Processing) chips.

TOSHIBA MICROSYSTEMS INC., 2000-2003

Sr. Verification Engineer

Excellent in test bench development, test cases generation and RTL debug.

. RTL test bench and test case development for Set-Top-Box project,

including USB Device IPs.

. Designed Random Test Program Generator for Cryptographic IP's

(TDES/AESMD5/SHA1) using Perl & C programming languages.

. System level Software simulation and RTL debug.

INFINEON TECHNOLOGIES INC., 1997-2000

Sr. Verification Engineer

Good at automatic test environment setup, RTL & Gate level Software

simulation & debug, ISS simulation modeling.

. Developed an automatic testing environment for functional regression

verification for Micro-controller designs.

. I-Cache, Watchdog, GPT timer and random test development in Perl &

Assembly.

. Gate level SW simulation, production test vector generation and silicon

debug.

. Simulation model development in C (Watchdog Timer, General Purpose

Timers, System Timers) for Infineon's Instruction Set Simulator (ISS).

SUN MICROSYSTEMS INC., 1994-1997

Sr. Software Engineer

Software tools development & testing for UltraSparc product/test

engineering.

. Efficiently processed Simulation vector or target ATE systems (MegaOne,

Schlumberger IS9000).

. Test vector format conversion tools design in C and Tcl/Tk.

. Developed various SAS database tools for Wafer Sort data analysis.

. Test team lead for Cadence's Test Synthesis tools, responsible for

Test plan generation, Verilog test case development, new engineers

training.

EDUCATION

M.S. Electrical & Computer Engineering, Arizona State University, Arizona,

USA

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