Engineer Development
Resume:
Lisa Phan
Austin, TX *****
Cell phone:
Home phone:
e-mail:
*********@*****.***
HIGHLIGHTS OF QUALIFICATIONS:
. Professional experience in Network Processor verification, SoC
verification, Memory controller verification
. Extended experience in verification, both at the block/unit-level and at
the full-chip-level
. Developing Verilog and SystemVerilog testbenches
. Writing bus monitors and checkers in Verilog and SystemVerilog
. Development and execution of test plans
. Strong problem-solving and debugging skills
. Extended knowledge in AMBA bus- AXI, AHB, APB
. Experience in ASIC design for data flow controller
Skills:
Familiar with the use of the following tools for design verification:
- Synopsys VirSim, DVE
- Programming in C, Verilog, SytemVerilog, Perl
WORK EXPERIENCE:
Verification Engineer
Network Processor Group, LSI
3/2004 - Present
Developed the new verification methodology/flow for the SoC.
. Development of unit testbench using SystemVerilog to verify the Back-
Pressure Agregator.
. Development of unit SystemVerilog testbench for AXI bus to verify DDR
memory controller
. Development a unit testbench to verify L1 Cache in Data Queue Engine
. Writing Coverage, BFMs, Transactors, and constrained Random Stimulus,
using channels as communication method to send data.
. Development of random tests using SystemVerilog
. Development of protocol checking using SVA
. Development of functional coverage (coverage point and coverage group)
. Writing manual tests to improve code coverage
. Working with Validation group to replicate the failing scenarios from
lab to simulation environment to help fixing RTL bugs.
. Running full regression and debugging the failing tests.
. Running gate simulation
Verification Engineer
Network Processor, AGERE
11/2000 - 2/2004
. Development of testbench drivers, monitors, stimulus, response
checkers using Quick Bench
. Development of test plan to verify SED and Output port
. Development of BFM using Verilog for third party usage
. Generated random tests and wrote directed test cases
. Ran regression and debugging failing tests
Verification Engineer
Micro-Controller, IBM
1/1998 - 10/2000
. Designed test plan, built Verilog testbench and write coverage
monitor.
. Generated testcases for core verification which included external
micro-controller function.
. Helped to verify PowerPC Execution unit, generated test plan, wrote
testcases, ran simulation.
Logic Design Engineer, ECC and Memory Controller
10/1995 - 12/1997
Storage Controller, IBM
ASIC design for Memory Controller.
. Designed memory controller to control data flow to/from Processor
Local Bus and External Memory with high performance of page/bank
hit/miss.
. Designed memory ECC which included single bit correction and double
bit correction with 32 or 64 bit address
. Wrote testcases for simulation and bring-up.
EDUCATION:
BS in Electrical Engineering University Of Arizona (UoA), Graduation
with honor
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