Sql Server Design

ASHWITHA KRISHNA KUMAR

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****, *. **** *****, #***, Chicago, IL 60616. (917)- 434 - 4314 ********@***.***

OBJECTIVE

Seeking an opportunity to do my Internship/ Co-Op in an Organization that will help me to put forth my

ideas based on the academic knowledge acquired so far and thereby have a good learning experience which will

enhance my future career endeavors.

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EDUCATION

M.S. Electrical Engineering Expected: May 2012

Illinois Institute of Technology (IIT), Chicago, IL

GPA:3.6/4.0

B.Tech Electronics and Communication Engineering

SASTRA University, Tamil Nadu, India April 2009

GPA: 8.65/10

CORPORATE EXPERIENCE

Oracle Financial Service Software Ltd.,- Business trainee, Pune, India Jan 2010– July 2010

Was trained for Database management system of Deustche Bank in SQL Server.

SKILLS

Synopsys Tools: Hspice, Nanosim Cadence Tools: Encounter RTL Compiler, Encounter Timing

Other Tools: Magic Layout Editor,Irsim, Modelsim, Matlab. FPGA & Microcontrollers: Altera Quartus II

Programming: C, C++, VHDL, Verilog, Database: SQL Server Operating Systems: Linux (Ubuntu), Windows Series

EXPERIENCE

IITV Technical Director, Illinois Institute of Technology, Chicago, IL Jan 2011- Present

Involves recording the live lectures taking place at IIT and posting them online for the aid of internet and

distance education students.

Technique to Interface Hardware and Software, IIIT, Bangalore, India Dec 2008 -March 2009

Design a FPGA as a slave and DSP Blackfin - BF 537 as the master a serial peripheral port interface was set

The FPGA was programed using the Altera Quartus II and the BF537 was programmed using Assembly

language.

Projects at Graduate level, IIT, Chicago

Design of CPU at the gate level using the Hardware Language Verilog and the simulations tools like IRSIm.

Optimized design of Cache using the Hardware language VHDl; which included the various

implementation Strategies for the Cache operation.

Worked on a project, whose objective is to design and characterize circuits using 45nm technology and

dualVt threshold transistor implementations. Cadence IC 6.1 tool is used for schematic entry, Synopsys

Hspice for simulation and Synopsys Nanosim for power analysis.

In- Plant Training - Reliance Communications LTD, Chennai, India June 2007

Worked in the Networking Department towards design of the basic Network Systems,

Certificate course - Embedded systems at SASTRA University, India, July 07 2007 - Sept 22 2007

Robotics Workshop by THE ROBOTICS INSTITUTE, Tamil Nadu, India Feb 2007

Activities

Participated in RUBE GOLBERG – 2010 contest conducted by GANGREEN association of IIT, Chicago.

Active participant of intramural cultural event (CARPE DIEM) in college and also in Oracle financial services

cultural event (iCE). 3 times winner in the group dance event Organized in college.

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