Project Engineer
Resume:
Jeyanthi Arumugam
E-mail: ****************@*****.***
Contact: +91-978*******
Objective
Seeking fulltime position in the domain of Networking, Data Communications,
and Microprocessor based System design, Formal and Functional Verification
with the organization of high repute.
Professional Synopsis
8 years of experience in Networking, Data Communications, and
Microprocessor based System design, Formal and Functional Verification.
Presently associated as Senior Engineer with Infineon Technology, Singapore
Expertise in Constraint-Driven Test Generation with data, Temporal
Checking, Functional coverage and Formal Verification tools
Worked on Assertion based Verification IP (AIP) using OVA, SVA, CBV
(Freescale Proprietary), Magellan (Synopsys), IFV (Cadence)
Worked on Logical Equivalence check between RTL and Synthesized RTL
(Synthesis done using RTLComplier (Cadence) and Design Complier (Synopsys))
Programming and modelling verification environment in high level languages
Knowledge in all aspects of Design Life Cycle through Specification, Design
Engineering, Modeling, Integration, Verification, Documentation, including
Code Documentation and Maintenance.
Knowledge Purview
Operating System : DOS, Windows, UNIX, Linux, Solaris
Modelling Languages : Verilog HDL, OVA, SVA, SV, CBV,
Assembly
Scripting Language : Perl
Simulation Tools : VCS, VCSi, NC-Verilog
Verification Tools : Magellan ?1, Conformal Encounter
(LEC Cadence), IFV (Cadence), ICC (Cadence)
Version Control System : Clear Case, Design Sync
Software : C, C++, System C
Organisational Experience
1. Infineon Technology, Singapore
Senior Engineer (June 2010 - till date)
Project Title: SOC Level Verification for Automobile chip
Chief role entails:
. Verifying the Integrity of various IP's in SOC level
. Writing test case in System C to check the functionality in SoC level
. Implementing Monitors using System verilog Assertion
. Writing test plan and plan sign off
. Error Injection Stuff in SOC level
. Bus stressing and measuring the Performance metric
. Working on various BUS protocol like SRI, SPB etc on Soc level
. Developing Reference model for Internal IP's(FCE etc)
2. ST Microelectronics Pvt Ltd, Singapore
Senior IC Design Engineer (Feb, 2009 - June 2010)
Project Title: ISP level Verification for 3 Mega Pixel Imaging
project with Video Model Receiver
Chief role entails:
. Verifying various IP's of ISP pipe
. Setting up Register value and integrating the IP's in Verification
Environment
. Running Register Bist Test
. Running Patch test and NVM test
. Integrating assertions for various IP's
. Coding assertions on Digital and Analog interfaces
. Providing Scripts for Bench level testing
. Through Firmware, testing hardware simulation
. Setting up Regression environment
. Worked on Verification of IP's like Binning Repair, Antivegnets,
Dither, Scaler, Derate, Jpeg and Video Models
. Worked on I2C protocol, ITU601 and ITU656 video protocols
Project Title: ISP level Verification for 5 Mega Pixel Imaging
project with Video Model Receiver
Chief role entails:
. Verifying various IP's of ISP pipe
. Setting up Register value and integrating the IP's in Verification
Environment
. Running Register Bist Test
. Coding Firmware test case, Running Patch test and NVM test
. Integrating assertions for various IP's
. Coding assertions on Digital and Analog interfaces
. Providing Scripts for Bench level testing
. Through Firmware, testing hardware simulation
. Setting up Regression environment
. Worked on I2C protocol, ITU601 and ITU656 video protocols
. Worked on Post layout Net list with timings (Both best case and worst
case), and with no timings
2. Freescale Semiconductor Pvt Ltd, Noida, India
Senior Design Engineer (March, 2006 - Jan 2009)
Involved in RTL Verification.
Involved in verification plan development for platform (ARM BASED).
Setting-up Gate level verification flow.
Handling test bench modification as per project needs.
AXI to IPS IP verification.
Constraint based verification of AXI to IPS IP.
Project Title: Platform Level Verification of ARM1176 (ARM JFS- RISC
processor) for SoC (System on Chip) of Zappa.
Role of ARM1176 Platform:
Provides an environment for ARMJFS processor and connection with
external memory and integrate it into SoC Design.
Chief role entails:
. Coding and Developing Assertions using SVA for various blocks of
ARM1176 platform.
. Coding and Developing Assertions using SVA for standalone Block Amba
AXI2IPS.
. Writing and developing Coverage Plan for ARM1176 Platform.
. Writing new test cases to meet the 100% coverage.
. Writing test cases to cover all the corner case scenarios of ARM1176
platform.
. Performed Logical Equivalence Check (Rtl vs. Synthesized Rtl) on
various block of ARM1176 platform and reported the floating node and
functionality issues caught using LEC.
Targets:
. Functional Coverage.
. Regression Clean with SVA ON (VCS and NCVerilog).
. Correctness Assertion clean
. Meeting all requirements and Deadline specifications.
. Given Support for LEC, SVA (platform level), AXI2IPS module.
. LEC clean (Rtl Complier and Design Complier).
Team Size:
1 (Complete responsibility for Assertions, LEC)
Project Title: Platform level verification of ARM1136 for SoC (System on
Chip) of SkyeLT
Role of ARM1136 Platform of SkyeLT:
Provide an environment for ARMJFS processor and connection with
external memory and integrate it into Soc Design.
Chief role entails:
. Coding and Developing Assertions using CBV for various blocks of
ARM1136 platform of SkyeLT SOC.
. Writing and developing Coverage Plan for ARM1136 Platform of Skye LT.
. Writing new test cases (using Assembly and verilog) to complete the
existing Coverage.
. Writing test cases to cover all the corner case scenarios of ARM1136
platform.
. Logical Equivalence check on various blocks of ARM1136 platform (RTL
vs. Netlist), Comparison of platform (RTL vs. RTL) and Comparison
between platforms (Skye plus Rtl and SkyeLT Rtl.)
Targets:
. Functional Coverage.
. Regression Clean with CBV Monitor ON (VCS and NCVerilog).
. Assertion clean
. Meeting all requirements and Deadline specifications.
. LEC clean (Rtl Complier and Design Complier).
. Given Support for LEC, CBV.
Team Size
Single person completely involved for Assertions, LEC, and CDC.
Project Title: Platform level verification of ARM1136 for SoC (System on
Chip) of Skye XPA
Role of ARM1136 Platform of Skye XPA:
Provide an environment for ARMJFS processor and connection with
external memory and integrate it into Soc Design.
Chief role entails:
. Coding and Developing Assertions using CBV for various blocks of
ARM1136 platform of Skye XPA SOC.
. Writing and developing Coverage Plan for ARM1136 Platform of Skye XPA.
. Writing new test cases (using Assembly and verilog) to complete the
existing Coverage.
. Writing test cases to cover all the corner case scenarios of ARM1136
platform.
. Logical Equivalence check on various blocks of ARM1136 platform (RTL
vs. Netlist), Comparison of platforms (RTL vs. RTL) and Comparison
between platforms(Skye Plus Rtl and Skye XPA Rtl)
. Clock Domain crossing check on complete Platform of ARM1136.
. Complete responsibility for test bench Integration as per RTL
releases.
. IFV run on Amba AHB2IPS.
Targets:
. Functional Coverage.
. Regression Clean with CBV monitor On (VCS and NCVerilog).
. Assertion clean
. Meeting all requirements and Deadline specifications.
. LEC clean (Rtl Complier and Design Complier).
. Test bench release as per RTL release.
. Given Support for LEC, CBV.
Team Size
Single person completely involved for Assertions, LEC.
Project Title: Platform level verification of ARM1136 for SoC (System on
Chip) of RINGO
Role of ARM1136 Platform of RINGO:
Provide an environment for ARMJFS processor and connection with
external memory and integrate it into Soc Design.
Chief role entails:
. Ported Assertions as per requirement of ARM1136 platform of RINGO SOC.
. Writing and developing Coverage Plan for ARM1136 Platform of RING0.
. Involved in correcting patterns and Assertions as per Regression
failures.
. Logical Equivalence check on various blocks of ARM1136 platform (RTL
vs. Netlist), Comparison of platforms (RTL vs. RTL).
. Involved in initial work around in gate level simulation.
. Validating CBV failures.
Targets:
. Functional and Code Coverage.
. Regression Clean with CBV monitor On using (VCS and NCVerilog).
. Assertion clean
. Meeting all requirements and Deadline specifications.
. LEC clean (Rtl Complier and Design Complier).
Team Size
Single person completely involved for Assertions, LEC.
Given Support for LEC, CBV until platform tapeout
Project Title: Platform level verification of ARM926 for SoC (System on
Chip) of SENNA
Role of ARM926 Platform of Senna:
Provide an environment for ARM926EJS processor and connection with
external memory and integrate it into Soc Design.
Responsibility:
. Test bench ownership
. Regression, suite setup and environment stability
. Test bench changes as per Design requirement
. Test bench changes to incorporate CBV.
. Re-generated RDT patterns for few modules.
. GLS setup and changes as per the project requirement
. Coding and developing CBV as per platform requirements and obtain 100%
coverage.
. LEC run on individual blocks of ARM926 blocks and on platform level of
Senna.
. Developing Assembly and BFM patterns for Senna ARM platform
Team Size
Completely involved for Verification of Senna and leading
verification with the team of 1.
Have met all the deadlines.
Project Title: Module level verification of Event Adaptor for Emerald
Platform
Role and Responsibility:
. Writing assertion for Event Adaptor using System Verilog Assertion
. Achieving functional coverage, Code coverage using ICC ( Cadence).
. Taking to formal verification.
Team Size:
Single
Project Title: EVB Validation of ARM926 based SOC (Senna) (currently
working)
Role and Responsibility:
. Writing Patterns
. Configuring the board
. To run pattern on the EVB
3. Synopsys (India), Bangalore.
Individual Consultant (Since Mar 2005 to Mar 2006).
Project Title: Developing Benchmark System for Magellan
Role of Magellan:
Developing and Installing Test cases in the Atria system (Clear
case).These Test cases are used in the Regression System for the new
releases of Magellan.
Chief role entails:
Creating project files in the Tcl script using Magellan switches,
creating command for RTL, OVA, and SVA Assertions.
Removing bugs related to RTL code. These script files are run in
Magellan and the properties are checked for proven, falsified and bounded
proofs.
These test cases are then installed in the atria system.
Targets
. Regression clean
. Proven and coming up with new version of Magellan.
. Around 500 test cases installed in atria and have reported many bugs.
. Was appreciated by the Synopsys Manager.
Team Size:
Single
4. Silicon Interfaces (India).
Verification Engineer (Since 2003 to March 2005)
Project Title: Verification of RapidIO( Physical Layer Interface using OVA
and Magellan
Role of RapidIO Physical layer Interface:
. Developing Assertions in OpenVera Assertions (OVA) Language
. Generation of Random Test Stimuli on Magellan using Assertions
. Complete Verification of RapidIOTM Physical Layer Interface
Chief role entails:
Extensive Verification using Magellan and sign-off of all OVA Checkers
Extensively involved in the final documentation
Targets
. Regression clean
. Assertions clean and through Magellan Proven
Team Size:
3 Members involved actively.
Project Title: SI11RI10 RapidIO( Physical Layer Interface Core Verilog
Testing.
Role of RapidIO Physical layer Interface:
Study of the RapidIO( specifications for the above Physical Layer Interface
Core and was mainly involved in detailed Functional Verification of the RTL
core.
Chief role entails:
Involved for writing Test Benches including generation of possible
test vectors
Maintaining bug report
Targets:
Regression clean
Team Size:
3 Members involved actively.
Project Title: RapidIO( Physical Layer Interface Open Vera Assertions IP
Role of RapidIO Physical layer Interface:
The RapidIO Physical Layer Interface OpenVera Assertions based
VIP provides a concise declarative mechanism to code the specifications of
RapidIO Physical Layer Interface
in the form of sequences of events. This RapidIO OVA protocol
rule checker IP can work in a standalone mode i.e. can be plugged in any
design verification environment, which
uses the standard RapidIO Specifications without disturbing the
internal structure.
Chief role entails:
. Involved in the drafting of the RapidIO( Physical Layer Interface OVA
Proposal.
. Implementation of some of the Checkers in OpenVera Assertion Language.
Targets:
. Functional and Code Coverage.
. Regression Clean
. Assertion clean
. Meeting all requirements and Deadline specifications.
Team Size
Two people completely involved for Assertions using OVA.
Project Title: Cache Memory System
Role in Cache memory system:
Development of a Cache Memory System from Data Sheet to structural
code
Chief role entails:
. Carried out complete testing for the functionality of Cache
controller.
. Performed all policies of cache and locked down access.
. Performed Locked down access on various tags.
Targets:
. Meeting all requirements and Deadline specifications.
Team Size
Three people completely involved.
Training Programs Attended:
. Attended training sessions on OVA, Magellan, SVA, SV, and IFV, LEC.
. Certified in ST university program Job Effectiveness, Team
Effectiveness
Education:
. B.E. Electrical and Electronics Engineering, Kalasalingam University,
Srivilliputur, India (77 %)
. M.E. Applied Electronics, Coimbatore Institute of Technology,
Coimbatore, India (89%)
Reference:
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