Design Project

WEI ZHANG

Address: *** ******* **., *********, ** Phone: 617-***-****

Email:********@**.***

Objecti M.S. C.E. candidate seeks internship or full-time position to apply and to

ve: enhance skills in embedded system design and hardware circuit design.

Educati Boston University, Boston, MA

on: 2011

M.S. in Computer Engineering candidate in September, 2011

GPA: 3.3/4.0

Beijing Jiaotong University, Beijing, China

2009

GPA: 3.4/ 4.0

B.S. in Communication Engineering

Skills: Computer Skills: Nios IDE, Xilinx ISE, Cadence Development Kits (Cadence

Verilog XL, Cadence Encounter, etc.), HSpice, Multisim, Qt Development Kits,

MATLAB, C, C++

School Boston University, Boston, MA

Project Compact Biosensor for Point of Care Diagnostics

s: 2011

Built a self-contained, compact, battery operated, and robust biosensor for

dengue fever diagnosis based on Freescale's CPU08 MCU.

Utilized CodeWarrior platform to write code to control the scan modes of the

sensor and talk with PC host via Bluetooth.

Multiple Input Multiple Output Receiver:

Integer-Forcing Linear MIMO Receiver Design (ASIC Design)

2011

Utilized Cadence kits to design a new framework for MIMO decoding based on

integer-forcing linear algorithm, which keeps a low complexity while has a

better performance than common linear receivers.

Used verilog to do RTL design, optimized the data throughput and power

consumption.

Embedded System Design Course:

Design of a portable game utilizing the Gumstix Vertex board and a Samsung LCD

touchscreen 2010

Used Qt development platform for Linux to design a snake game GUI.

Compiled for Qt for Embedded Linux.

Cross-compiled the project for Embedded Linux and transferred to a Gumstix

board for execution.

VLSI Design Course:

Design of an 8-input-port x 8-output-port router using the 250 nm CMOS

technology 2010

Utilized Cadence design tool to draw circuit schematic for building a router.

Including the design of Input buffers (using SRAM cells), Arbiter (using round

robin priority), and Crossbar (using Omega networks).

Calculated the size of the transistors that used in the project to minimize

the power dissipation, and time delay.

Calculated the timing and simulated the Cadence result in circuit schematic.

FPGA Design Course:

Multi Frequency Implementation of the Quarter Wave Model on the FPGA

2009

Design the Quarter Wave Module using VHDL to determine Azimuth Angles for

every frequency response from the Analog Inner Hair Cell Auditory Nerve

Integrated Circuit (AIHCAN IC), which gathered the sample multiple-frequency

responses.

Design the display module to output the range of Azimuth angles both on the

LCD provided by the Virtex-5 FPGA as well as a monitor.

Beijing Jiaotong University, Beijing, China

Major Qualifying Project:

Design of Text-to-Speech System based on Xscale Platform

2008

Used Microsoft Embedded VC++ to design a TTS software GUI.

Collaborated with some Phd students to do research on speech synthesis

algorithm and design the database of speech for WinCE.

Cross-compiled the project for WinCE and transferred to the Liod Xscale

Platform.

Work Beijing Hopes Innovative Technologies Co. Ltd., Beijing, China

Experie

nce: Program tester

11.2008 - 5.2009

Work as an intern software tester in the technical department, cooperate with

other engineers to design and develop the Face Recognition Attendance System.

Analyzed of functional requirement of the system.

Wrote software design document and finished the analysis report.

Affilia Member of the Student Association of Graduate Engineers (SAGE)

tion:

Languag Fluent in English, Mandarin

e:

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