Project Engineer
Resume:
Ankita Choudhary
Email: *******@********.**
**, ******* ****** *****, ***** No: 289-***-****
Hamilton - L8P4J9,
ON, Canada.
Profile
Multi-skilled professional with 2.5 years of experience as Project Engineer specializing in sustainable infrastructure. I have
developed a strong work ethic and approach every problem with professionalism and zeal which allows me to bring my
outgoing personality and strong interpersonal skills to bear.
Education
o Masters in Engineering Design Expected
completion August 2013
McMaster University
Hamilton, Ontario
Canada
o Bachelor of Technology 2005 - 2009
Electronics & Telecommunication, 86% aggregate
KIIT University
India
Recent Projects
Storm-water management for a residential complex May 2013 –
Present
o Working as a Summer Intern with the City of Hamilton to develop a storm-water management plan for an upcoming
residential area at the Hamilton Waterfront (Pier 8).
LRT Station Sep 2012 – Apr 2013
o Also worked in a team of 4 on designing a LRT station in Dundas, Hamilton and the affects it will have on the
surrounding area. In this project we are suppose to select a suitable location for the station thereby improving the
current transportation problem.
Building a Sustainable Rooftop Sep 2012 –
Dec 2012
o Worked in a team of 4 on designing a Sustainable Rooftop at Jackson Square mall in downtown Hamilton and thereby
creating a sense of place, keeping in mind parameters of ‘Triple Bottom Line’ and bringing them into practice. By the
end of this project we hope that it will not only improve the economic development of the mall but will also act as a
place to improve people’s health.
Professional Experience
WIPRO Technologies, India Jan 2010 – July
2012
Experience in the Board design as a Project Engineer covering the following aspects:
o Design Validation & Testing
o Timing Analysis
o Schematic Entry
o Test plan preparation
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o Board Bring-up/debugging
o Power Analysis
Having experience/exposure with various languages/tools:
o Lab equipment : Oscilloscope, logic analyzer, Function generator
o EDA TOOLS - Mentor Graphics DxDesigner, Cadence Allegro PCB editor, Cadence-Orcad schematic entry, Xilinx
ISE 9.1c
Technical Exposure:
Programming Languages & Softwares : C, C++, VHDL, Verilog, Matlab
Project 1: Avaya (Nortel) Sustenance May 2010 - Dec 2010
This project was on the sustenance of already existing telecommunication boards which includes line cards (analog and digital),
XCMC cards, MG-XPEC cards. I was working in a team of 9 members.
Responsibilities
Validation of Test Plan involving various interfaces
o
Pre-layout SI Analysis
o
o Alternate component(s) Selection
o Interaction with customers
o Interaction with component procurement team
o Review of documents
o Test plan design
o Board bring up and debugging
o Coordination with mechanical and software teams
Tools used:
o Oscilloscope, logic analyzer and function generator
o Software used: DDMEz, PartSmart
Project 2: CRBU-Pb free conversion and Library SEZ Development (CISCO) Jan 2011 -
July 2012
This project was based on converting schematics of leaded boards to lead free and creating lead-free logic symbols for the same.
I was working in a team of 5 members.
Responsibilities
o Pb free symbol creation requests
o Conversion of leaded schematics to lead free.
o Review of documents
o Coordination with the library team
o Footprint Validation
o Creating logical lead free symbols
Tools used:
o DxDesigner (EPD 2005)
o Allegro (version 15.7/ 16.3)
Trainings:
2
o 3 months training (Jan 2010 – March 2010) in System Design provided by Wipro Technologies
for new employees.
o 1 month training (May 2007) in V.L.S.I at VEDANT (Semiconductor Complex Ltd), India
Language of implementation: VHDL using MODEL SIM, XILINX 9.1c
References available upon request
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