| Resume alert | Resumes 61 - 70 of 119 |
Project Security
Pune, MH, India
... EDUCATIONAL QUALIFICATION Degree College University Percentage Year M.E.(VLSI&ES) G.H.Raisoni College Of Engg and Management, Wagholi,Pune Pune 8.48 credit 2014-15 B.E. (ENTC) P.E.S. Modern College of Engineering, Pune Pune 64.46% 2013 H.S.C. S.P. ... - 2015 Aug 07
... EDUCATIONAL QUALIFICATION Degree College University Percentage Year M.E.(VLSI&ES) G.H.Raisoni College Of Engg and Management, Wagholi,Pune Pune 8.48 credit 2014-15 B.E. (ENTC) P.E.S. Modern College of Engineering, Pune Pune 64.46% 2013 H.S.C. S.P. ... - 2015 Aug 07
Engineer Project
Pune, MH, India
... 3] Project name: To generate high frequency PWM channels with different characterstics using FPGA.(fourth year) Domain : VLSI + EMBEDDED Project Details : The main project intends to generate variable dutycycle and high frequency PWM signals for ... - 2015 Aug 01
... 3] Project name: To generate high frequency PWM channels with different characterstics using FPGA.(fourth year) Domain : VLSI + EMBEDDED Project Details : The main project intends to generate variable dutycycle and high frequency PWM signals for ... - 2015 Aug 01
Design Technical
Pune, MH, India
... - Design PCB - Design circuit - Making Eye blinking Sensor Experience • Fresher – 0 Experience Technical Area of Interest: - ELECTRONICS – VLSI Technology - Embbaded Technology Personal Details: Address TO – Devgam TA – Kunkavav PIN : 365460 Dis. :- ... - 2015 Jul 30
... - Design PCB - Design circuit - Making Eye blinking Sensor Experience • Fresher – 0 Experience Technical Area of Interest: - ELECTRONICS – VLSI Technology - Embbaded Technology Personal Details: Address TO – Devgam TA – Kunkavav PIN : 365460 Dis. :- ... - 2015 Jul 30
Design Tech
Pune, MH, India
Address: Yashaswini P R D/O Rangegowda P R #LIG 441,28th cross, KHB layout Opposite new busstand Chanpatna Ph - 948-***-**** Hassan-573201 Qualification: M.tech(persuing) VLSI Design and Embedded systems RIT, Hassan Interest : Analog design, ... - 2015 Jul 14
Address: Yashaswini P R D/O Rangegowda P R #LIG 441,28th cross, KHB layout Opposite new busstand Chanpatna Ph - 948-***-**** Hassan-573201 Qualification: M.tech(persuing) VLSI Design and Embedded systems RIT, Hassan Interest : Analog design, ... - 2015 Jul 14
HTML, CSS, Core Java, J2EE, Android
Pune, MH, India
... 3) Clap Operated Switches Diploma Technology: VLSI Turning switches ON/OFF using claps. Educational Qualification: PGDM (Wireless & Mobile Computing): C-DAC Mumbai - 2013 - 55.63%. B.E. (Electronics & Telecommunication): Priyadarshini College of ... - 2015 Jun 30
... 3) Clap Operated Switches Diploma Technology: VLSI Turning switches ON/OFF using claps. Educational Qualification: PGDM (Wireless & Mobile Computing): C-DAC Mumbai - 2013 - 55.63%. B.E. (Electronics & Telecommunication): Priyadarshini College of ... - 2015 Jun 30
Engineer Summer Training
Pune, MH, India
... Core Competencies: Transmission control protocol, Internal protocol, Network Analysis System, Signal System, VLSI, Wireless Communication, Digital Electronics, Data Communication Network, Principle of Communication and Integrated Circuit. EDUCATION: ... - 2015 Jun 29
... Core Competencies: Transmission control protocol, Internal protocol, Network Analysis System, Signal System, VLSI, Wireless Communication, Digital Electronics, Data Communication Network, Principle of Communication and Integrated Circuit. EDUCATION: ... - 2015 Jun 29
Engineering Project
Pune, MH, India
... Languages : C, C++ Tools : Matlab, Xillinx Curriculum Projects: Engineering Project: Duration : 1 year Title : “FFT Implementation By FPGA Using VEDIC Mathematics” Technology : VLSI Description : FPGA is implemented using vedic algorithm. ... - 2015 Jun 27
... Languages : C, C++ Tools : Matlab, Xillinx Curriculum Projects: Engineering Project: Duration : 1 year Title : “FFT Implementation By FPGA Using VEDIC Mathematics” Technology : VLSI Description : FPGA is implemented using vedic algorithm. ... - 2015 Jun 27
Engineering Design
Pune, MH, India
... Board SPARTAN -3 PG-DIPLOMA in VLSI at CDAC PUNE current) In depth analysis of the simulators, synthesizers and verification using tools like questasim, modelsim, Xilinx ise .Completed my vlsi languages like VHDL & Verilog. Trained in both of these ... - 2015 Jun 22
... Board SPARTAN -3 PG-DIPLOMA in VLSI at CDAC PUNE current) In depth analysis of the simulators, synthesizers and verification using tools like questasim, modelsim, Xilinx ise .Completed my vlsi languages like VHDL & Verilog. Trained in both of these ... - 2015 Jun 22
fresher in embedded and VLSI
Pune, MH, India
... Warje M.E Embedded &VLSI May 2015 1st year 7.50 CGPA First Shivaji University, Kolhapur Bharti Vidyapeeth Engg.College. Kolhapur B.E Electronics May 2011 73% Distinction Kolhapur Board Bharati Vidyapeeth, Kadegaon. H.S.C. March 2007 68% First ... - 2015 Jun 07
... Warje M.E Embedded &VLSI May 2015 1st year 7.50 CGPA First Shivaji University, Kolhapur Bharti Vidyapeeth Engg.College. Kolhapur B.E Electronics May 2011 73% Distinction Kolhapur Board Bharati Vidyapeeth, Kadegaon. H.S.C. March 2007 68% First ... - 2015 Jun 07
Design Assistant
Pune, MH, India
... Sharma et al, “Estimation of Inter-Symbol Interference using Clock Pattern ” in 19th International VLSI Design and Test Symposium (VDAT 2015). (Accepted) • V. K. Sharma et al, “A Comparative Analysis of Jitter Segregation Techniques ” in ... - 2015 Apr 16
... Sharma et al, “Estimation of Inter-Symbol Interference using Clock Pattern ” in 19th International VLSI Design and Test Symposium (VDAT 2015). (Accepted) • V. K. Sharma et al, “A Comparative Analysis of Jitter Segregation Techniques ” in ... - 2015 Apr 16