Curriculum Vitae

Vijender Kumar Sharma

IIIT-Delhi

M-133, Street No.-08, Shastri Nagar, Delhi.

Email: aco7sj@r.postjobfree.com

Mobile Number: +91-991*******

PUBLICATIONS/BOOKS

• V. K. Sharma et al, “Estimation of Inter-Symbol Interference using Clock Pattern ” in 19th

International VLSI Design and Test Symposium (VDAT 2015). (Accepted)

• V. K. Sharma et al, “A Comparative Analysis of Jitter Segregation Techniques ” in International Conference on Electronics, Communication and Computational Engineering (ICECCE), 2014.

• Monograph “Analysis and Estimation of Jitter Sub-components ” by Lambert Academic Publishing, Germany, 2014.

PROFESSIONAL EXPERIENCE

Company Name Position Duration

STMicroelectronics, India Research Engineer Oct, 14 – Present.

STMicroelectronics, India Intern July, 13 – June, 14.

IIIT-Delhi Teaching Assistant Aug, 12 – June, 13

Vivekananda polytechnic college Lecturer July, 11 – June, 12.

EDUCATIONAL QUALIFICATIONS

M.Tech in VLSI & Embedded System (July, 2014)

IIITD, Delhi, India

Thesis: Analysis and Estimation of Jitter Sub-Components (Advisor: Dr. Sujay Deb)

CGPA: 8.62

B.Tech. in Electronics and Communication Engineering (June 2011)

Rajasthan Technical University, Kota, India

Undergraduate Thesis: Speed Checker on Highways (Advisor: J.P. Sharma)

Percentage: 70.25 (Honors)

TECHNICAL ELECTIVES

Introduction to VLSI design

Analog circuit design

VLSI design and test flow

RF design

Memory design and testing

Advanced signal processing

System on chip design and testability

Probability and random process

PROJECTS UNDERTAKEN

• Jitter Generation and its Analyzer for High Speed Serial Link Characterization (On going)

Description: Designing an IP having both jitter generation circuit for receiver testing and jitter analyzer circuit for

BER calculation. PLL is main building block for jitter generation. To avoid extra circuitry in the jitter test set-up, jitter

generation mechanism is done by PLL itself. The project is designed from the transistor level (FDSOI Technology, 28

nm). Further, analytical expression for on chip power supply variation is obtained.

Tools: Agilent ADS, Cadence Virtuoso, Mentor Graphics (ELDO).

• SRAM with sleep transistors, power issues to be resolved.

Description: Reduces the sub-threshold leakage power using the Sleep Transistors in the SRAM memory design.

Tools: Cadence Virtuoso, Mentor Graphics (ELDO).

• Block based compressive sensing.

Description: A review work on Block based compressive sensing including their different types of reconstruction

algorithm for still images and videos.

Tools: MATLAB

• DVFS for Optimal Performance of SOC

Description: DVFS is the technique that is used to reduce dynamic energy dissipation by lowering the Supply Voltage

and Operating Frequency.

Tools: MATLAB Simulink, Cadence Virtuoso

M. Tech THESIS

• Analysis and Estimation of Jitter Sub-Components.

Description: Jitter is most crucial issue of signal integrity. It is the deviation of transition edge of signal

from their ideal position. It causes setup and hold time violation in the circuit.

The objective of this is to design an algorithm to estimate all the jitter components present in the signal

to reduce/negate the effect of this on the signal.

The second objective of thesis is to do improvement in existing jitter segregation algorithm.

TECHNICAL PROFICIENCY

HDL & PROGRAMMING LANGUAGES Verilog, C.

OPERATING SYSTEMS MS-DOS, Windows variants, Linux/Unix variants.

TOOLS AND TECHNOLOGIES MATLAB, Advanced Design System. Xilinx,

Cadence(Virtuoso), Mentor graphics (Eldo).

POSITIONSOF RESPONSIBILITY

Tresurer at IEEE student chapter at IIITD.

AWARDS AND ACHIEVEMENTS

1. Participated in “National Symposium on Biodiversity Conservation and Environmental Biotechnology” where I presented a paper on the topic “Microwave Remote Sensing”.

2. Won many prizes in school level competitions.

3. Won many prizes in intra college dance competition.

4. Short listed in Electra quiz event in decade convergence of our college.

5. Participated in various college sports.

6. GATE Cracked in 2011 and 2012.

INTERESTS AND HOBBIES

• Intellectual Debates.

• Teaching.

• Chess.

REFERENCES

1. Dr. Sujay Deb 2. Dr. Jai Narayan Tripathi

Assistant Professor Senior Design & Research Analyst

IIIT-Delhi STMicroelectronics, India

Mail: aco7sj@r.postjobfree.com Mail: aco7sj@r.postjobfree.com

Mobile: +91-971******* Mobile: +91-783*******

DECLARATION

I hereby declare that the above-mentioned information is correct up to my knowledge and I bear the

responsibility for the correctness of the above-mentioned particulars.

Vijender Kumar Sharma Place Delhi

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