| Job alert | Jobs 1 - 10 of 19 |
Mixed Signal ASIC Design Lead - System Verilog
ACZ Global Private Limited
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Pune, Maharashtra, India
... - Successful realization of more than 5 ASIC designs - In depth knowledge of Cadence custom IC EDA tools - Proficiency in system and behavioural modeling using MATLAB, System Verilog, Verilog-A/AMS. - Experience with HDL languages Verilog and/or ... - May 01
Lead - Mixed Signal/ASIC Design
ACZ Global Pvt Ltd
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Pune, Maharashtra, India
... - Successful realization of more than 5 ASIC designs - In depth knowledge of Cadence custom IC EDA tools - Proficiency in system and behavioural modeling using MATLAB, System Verilog, Verilog-A/AMS. - Experience with HDL languages Verilog and/or ... - May 07
Principal Engineer, Design Verification (USB, UVM)
Marvell
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Pune, Maharashtra, India
... Hands on experience in developing, updating, and debugging of Verilog, SV-UVM, SOC level testbenches is a must. Must have executed SoC/Subsystem/Block level Verification projects with hands on experience in USB based design verification Very Good ... - May 17
Sr. Staff Manager, Design Verification
Marvell
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Pune, Maharashtra, India
... Hands-on experience in System Verilog and UVM Hands-on experience with complex subsystems such as PCIE, NVMe, and NAND and standard AMBA interfaces such as APB, AHB, AXI. RTL design experience is a plus #L1-RS1 Additional Compensation and Benefit ... - May 10
Design Eng 5 - LPQ
Lattice Semiconductor Corp.
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Shivaji Nagar, Maharashtra, 411016, India
... The qualified candidate will be an expert in RTL design, best-in-class coding styles, algorithms, and both Verilog and System Verilog. The position will exercise many standard tools including Verilog simulations, lint, CDC; and will extend into ... - May 08
ASIC Digital Design, Sr Staff Engineer
Synopsys India Private Limited
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Pune, Maharashtra, India
... Experience of functional verification flow, Verification tools, and methodologies VMM, OVM/UVM and System Verilog Experience with System Verilog Assertions, code and functional coverage implementation and review Fundamental knowledge of Analog and ... - Apr 26
Field Programmable Gate Array Engineering Specialist
Baker Hughes
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Balewadi, Maharashtra, India
... Demonstrate good logic design concepts and computer design Be proficient in Verilog, VHDL and have had exposure to industry simulators Be able to build expertise in front end RTL design flow steps like lint, CDC, STA etc Work in a way that works for ... - May 08
Senior Embedded Software Engineer
QUASAR SOFTWARE DEFINED RADIO
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Pune, Maharashtra, India
... Understanding of FPGA HDL (VHDL, Verilog, System Verilog) and/or FPGA PL/RTL. Experienced in RTOS principles and concepts & hands-on experience in any RTOS. Prior System on a Chip (SoC) product development experience. Good understanding of cellular ... - May 21
Senior Engineer_FPGA
eInfochips (An Arrow Company)
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Pune, Maharashtra, India
Job Title: Senior Engineer - FPGA Location: Pune Experience level: 6+ Years In depth knowledge with VHDL/Verilog/System Verilog, RTL design, FPGA design, and FPGA design tools. Complete FPGA development flow from logic design, place & route, timing ... - May 14
ASIC Digital Design, Staff Engineer
Synopsys
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Hadapsar, Maharashtra, 411028, India
... May include such items as Verilog/SystemVerilog development, functional simulation, constraint development, test planning, behavioral modelling, and verification coverage metrics (functional coverage and code coverage) Identify design problems, ... - May 15