| Distance: | Job alert | Jobs 1 - 10 of 5369 |
ASIC Design Engineer
SK hynix memory solutions America Inc.
–
San Jose, CA
... Responsibilities RTL design (Verilog/SystemVerilog) for IP based on existing module or new specifications. Collaborate, create clear documentation and communication with Design Verification, Silicon Validation, and Firmware teams to ensure design ... - Sep 09
Senior ASIC/VLSI Design Engineer - RTL, DFT & Bring-up
Retym Israel Ltd
–
Cupertino, CA, 95014
... Candidates should have over 5 years in digital design with strong Verilog/System-Verilog skills and educational background in electrical or computer engineering. This position allows creativity and independence in a cutting-edge environment. #J ... - Sep 08
ASIC/VLSI Design Engineer Chip Design Full-time
Retym Israel Ltd
–
Cupertino, CA, 95014
... and apply them accurately in design.**Participate in all design stages **Micro-architecture definition*** **RTL coding (using Verilog/SystemVerilog)*** **Synthesis-friendly coding and timing-aware design Collaborate cross-functionally **Verification ... - Sep 08
Back Button
InnoGrit
–
San Jose, CA, 95112
... roles What You'll Be Doing Design and develop microarchitectures for high-performance, low-power SoCs Implement RTL using Verilog/SystemVerilog Participate in architectural planning, design reviews, and technical decision-making Develop and optimize ... - Sep 08
Emulation Engineer - Hardware Prototyping (HAPS)
Etched
–
San Jose, CA
150000USD - 275000USD per year
... Strong SystemVerilog and Verilog, with a working understanding of what synthesizes well for FPGA and what doesn't. Solid C/C++ and Linux system development. Scripting fluency for automation — Python, TCL, shell. Comfort debugging failures you didn't ... - Sep 09
Sr./Staff /Sr. Staff Engineer, IP Design (ASIC)
SK hynix memory solutions America Inc.
–
San Jose, CA
... Experience in SystemVerilog/Verilog for RTL development and microarchitecture definition. Experience with Clock Domain Crossing (CDC), timing closure, synthesis flows or Gate Level Simulation(GLS). Preferred Qualifications Experience in PCle(Gen4/5 ... - Sep 09
Test Engineer
Link Consulting Services
–
Santa Barbara, CA
96600USD - 128800USD per year
... Job Qualifications: Minimum of a Bachelor's Degree in Electrical Engineering and 5+ years of related experience in testing electronic hardware systems Familiarity with Verilog, Xilinx ISE, Quartus FPGA development tools Working proficiency in C#, ... - Sep 09
DFT (Design For Test) Engineer
Etched
–
San Jose, CA
150000USD - 275000USD per year
... Proficiency in System Verilog and fluency with industry-standard EDA tools (e.g., Synopsys DFT Compiler, Cadence Encounter Test, Mentor Tessent). Scripting and automation experience using Python, Perl, or TCL to streamline DFT implementation and ... - Sep 09
FPGA Design Engineer
SAAZ
–
Camarillo, CA, 93010
... Key Responsibilities: Develop and implement FPGA firmware (VHDL or Verilog) for image sensor control, high-speed data acquisition, synchronization, and real-time processing. Interface directly with visible and infrared (SWIR, MWIR, LWIR) sensors, ... - Sep 08
ECC Design Engineering Intern
SK Hynix Memory Solutions America Inc.
–
San Jose, CA
... Responsibilities Perform work on running FPGA System and collecting data for performance Perform design database management in GIT Should be able to code RTL logic with Verilog syntax. Should be able to run simulation using Synopsys VCS. Should be ... - Sep 08