| Resume alert | Resumes 11 - 13 of 13 |
Project Design
Visakhapatnam, 530001, India
... Knowledge in Synthesis and Static Timing Analysis. Digital Design, FSM,CMOS Circuits. Experience in CADENCE EDA tools like: NCVerilog, NCSim, SimVision, RTL Compiler. AREA of INTEREST: Circuit Designing and VLSI. Programming in VERILOG. PROJECT & ... - 2016 Feb 23
... Knowledge in Synthesis and Static Timing Analysis. Digital Design, FSM,CMOS Circuits. Experience in CADENCE EDA tools like: NCVerilog, NCSim, SimVision, RTL Compiler. AREA of INTEREST: Circuit Designing and VLSI. Programming in VERILOG. PROJECT & ... - 2016 Feb 23
Engineer Engineering
Visakhapatnam, AP, India
... As a benchmark, synthesis results have been provided for Altera Cyclone II series of FPGA devices. 64-bit ALU 3 VHDL The main aim of this project will be to using VHDL design a 64-bit ALU using VHDL module. It module is used to perform 32 operations ... - 2014 Sep 18
... As a benchmark, synthesis results have been provided for Altera Cyclone II series of FPGA devices. 64-bit ALU 3 VHDL The main aim of this project will be to using VHDL design a 64-bit ALU using VHDL module. It module is used to perform 32 operations ... - 2014 Sep 18
Chemical Engineer, Hands on experience in Process Engineering
Visakhapatnam, AP, 530017, India
... Office, MATLAB DCS: YOKOGAWA Operating System: Windows XP Professional, Windows 7 PROJECTS UNDERTAKEN: Major Project Title:SYNTHESIS OF BIODIESEL FROM NON EDIBLE OILS Place: MVGR College of Engineering, Vizianagaram Time taken: 90 days Description: ... - 2013 Jul 04
... Office, MATLAB DCS: YOKOGAWA Operating System: Windows XP Professional, Windows 7 PROJECTS UNDERTAKEN: Major Project Title:SYNTHESIS OF BIODIESEL FROM NON EDIBLE OILS Place: MVGR College of Engineering, Vizianagaram Time taken: 90 days Description: ... - 2013 Jul 04