| Job alert | Jobs 11 - 20 of 54 |
Senior Physical Design Engineer
Wipro
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Bengaluru, Karnataka, India
... Floor planning, Placement, CTS, Routing, STA, Power Integrity Analysis, Physical Verification. •Should have experience on Physical Design Methodologies and sub- micron technology of 28nm and lower technology nodes. •Should have experience on ... - May 31
Senior Physical Design Leads
Wipro
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Bengaluru, Karnataka, India
... Floor planning, Placement, CTS, Routing, STA, Power Integrity Analysis, Physical Verification. · Should have experience on Physical Design Methodologies and sub-micron technology of 28nm and lower technology nodes. · Should have experience on ... - May 25
Physical Design Engineer
Wipro
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Bengaluru, Karnataka, India
... Floor planning, Placement, CTS, Routing, STA, Power Integrity Analysis, Physical Verification. Should have experience on Physical Design Methodologies and sub-micron technology of 28nm and lower technology nodes. Should have experience on ... - May 25
ASIC Engineer, Implementation
Meta
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Bengaluru, Karnataka, India
... Develop Timing Constraints for RTL-Synthesis and PrimeTime-STA for the blocks and the top-level including SOC. Analyze the inter-block timing and come up with IO budgets for the various partition blocks. Develop Power Intent Specification in UPF for ... - Jun 03
Senior Physical Design Engineer
Sivaltech
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Bengaluru, Karnataka, India
... · Block level timing closure with sign off STA . · Block level ECO implementation involving netlist level logical changes. · Library performance analysis and fine tuning for implementation. · Excellent debugging skills in implementation issues and ... - Jun 18
Lead Physical Design Engineer
L&T Technology Services
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Bengaluru, Karnataka, India
... • Good knowledge of all PnR activities like Floor-planning, Placement, CTS, Routing, Timing closure(STA), signoff checks like FEV, VCLP, EMIR and PV. • Knowledge of industry standard EDA tools (Synopsys, Cadence, Mentor) • Worked on DSM technologies ... - Jun 18
Lead Static Timing Analysis & Sign-Off methodology Engineer
NXP Semiconductors
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Mathikere, Karnataka, 560012, India
Summary: STA & Sign off Methodology Engineer with min 6 years of experience with expertise in STA tools who can support timing and Power analysis & closure while making sure a seamless use of Foundation IP solutions. Responsibilities: The STA and ... - Jun 10
Sr.Physical Design Engineer
Tech Mahindra
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Bengaluru, Karnataka, India
... Floorplanning, placement CTS, Routing • Design planning (partitioning, bump planning & Routing) • Very good understanding of STA • Very good Debugging skill • Understanding about Analog block integration • Low power design >>Signoff checks • LEC ( ... - May 23
ASIC Static Timing Analysis Engineer
Google
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Bengaluru, Karnataka, India
... + Experience with STA sign-off constraint authoring for full-chip level, tape-out sign-off requirements, checklists, and associated automation. + Experience in one or more static timing tools: PrimeTime, Tempus, Timing Closure, STA, Timing ECO using ... - Jun 11
Lead Physical Design Engineer
Cognitive Design Technology Pvt Ltd
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Bengaluru, Karnataka, India
... shared NWELL methodology is highly desirable Experience in Cadence design flow is highly desirable/flat and hierarchical flow/STA timing signify/PV and PI signoff/ multi-bit flops/Retension flops Job Type: Full-time Benefits: Health insurance ... - Jun 05