| Resume alert | Resumes 1 - 3 of 3 |
Personal Details
Roorkee, Uttarakhand, India
**:** Gal a NE Se ll **% < GR < BIODATA NAME >: DEV VERMA PHONE No. : 827-***-**** APPLIED FOR : 10th PASS JOBS KKKKKKKKKKEKKREKRKKEKKERERKERERKERERERERKKKRK KKK WORK EXPERIENCE : No PERSONAL DETAILS : Father's Name : Mr. Anuj Verma Mother's Name : ... - 2020 Nov 27
**:** Gal a NE Se ll **% < GR < BIODATA NAME >: DEV VERMA PHONE No. : 827-***-**** APPLIED FOR : 10th PASS JOBS KKKKKKKKKKEKKREKRKKEKKERERKERERKERERERERKKKRK KKK WORK EXPERIENCE : No PERSONAL DETAILS : Father's Name : Mr. Anuj Verma Mother's Name : ... - 2020 Nov 27
Office Computer
Saharanpur, Uttar Pradesh, India
RESUME SHARMA ile: 707-***-**** se Vihar Colony, Nawada Road . $aharanpur s pma707839@gmail.c ng Sadan 2 challenging environment, seeing for an sxcalient opportunity (6 were. OFF al with my all interest and excellent skills * e High School passed ... - 2020 Sep 07
RESUME SHARMA ile: 707-***-**** se Vihar Colony, Nawada Road . $aharanpur s pma707839@gmail.c ng Sadan 2 challenging environment, seeing for an sxcalient opportunity (6 were. OFF al with my all interest and excellent skills * e High School passed ... - 2020 Sep 07
VLSI Trained Fresher
Saharanpur, UP, India
... Mentor Graphics: Modelsim SE 6.4 and 5.7 . Xilinx: Project Navigator 13.3 . Tanner EDA . Cadence NCSIM Verification in System-Verilog Environment . Hardware Description Languages: VHDL, Verilog . Hardware Verification Languages: System-Verilog(SV) . ... - 2014 Dec 31
... Mentor Graphics: Modelsim SE 6.4 and 5.7 . Xilinx: Project Navigator 13.3 . Tanner EDA . Cadence NCSIM Verification in System-Verilog Environment . Hardware Description Languages: VHDL, Verilog . Hardware Verification Languages: System-Verilog(SV) . ... - 2014 Dec 31